BibTeX records: Byong-Tae Chung

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@inproceedings{DBLP:conf/isscc/LeeKKKKPKKPSCKK14,
  author       = {Dong{-}Uk Lee and
                  Kyung Whan Kim and
                  Kwan{-}Weon Kim and
                  Hongjung Kim and
                  Ju Young Kim and
                  Young Jun Park and
                  Jae Hwan Kim and
                  Dae Suk Kim and
                  Heat Bit Park and
                  Jin Wook Shin and
                  Jang Hwan Cho and
                  Ki Hun Kwon and
                  Min Jeong Kim and
                  Jaejin Lee and
                  Kunwoo Park and
                  Byong{-}Tae Chung and
                  Sung{-}Joo Hong},
  title        = {25.2 {A} 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory {(HBM)}
                  stacked {DRAM} with effective microbump {I/O} test methods using 29nm
                  process and {TSV}},
  booktitle    = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
                  {ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
                  February 9-13, 2014},
  pages        = {432--433},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISSCC.2014.6757501},
  doi          = {10.1109/ISSCC.2014.6757501},
  timestamp    = {Mon, 09 Aug 2021 14:54:04 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/LeeKKKKPKKPSCKK14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/LeeSHBLLPCCCKCK14,
  author       = {Hyun{-}Woo Lee and
                  Junyoung Song and
                  Sangah Hyun and
                  Seunggeun Baek and
                  Yuri Lim and
                  Jungwan Lee and
                  Minsu Park and
                  Haerang Choi and
                  Changkyu Choi and
                  Jin{-}Youp Cha and
                  Jaeil Kim and
                  Hoon Choi and
                  Seung{-}Wook Kwack and
                  Yonggu Kang and
                  Jongsam Kim and
                  Junghoon Park and
                  Jonghwan Kim and
                  Jin{-}Hee Cho and
                  Chulwoo Kim and
                  Yunsaing Kim and
                  Jaejin Lee and
                  Byong{-}Tae Chung and
                  Sung{-}Joo Hong},
  title        = {25.3 {A} 1.35V 5.0Gb/s/pin {GDDR5M} with 5.4mW standby power and an
                  error-adaptive duty-cycle corrector},
  booktitle    = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
                  {ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
                  February 9-13, 2014},
  pages        = {434--435},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISSCC.2014.6757502},
  doi          = {10.1109/ISSCC.2014.6757502},
  timestamp    = {Mon, 10 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/LeeSHBLLPCCCKCK14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/SongLLHKCCK13,
  author       = {Junyoung Song and
                  Hyun{-}Woo Lee and
                  Soo{-}Bin Lim and
                  Sewook Hwang and
                  Yunsaing Kim and
                  Young{-}Jung Choi and
                  Byong{-}Tae Chung and
                  Chulwoo Kim},
  title        = {An adaptive-bandwidth {PLL} for avoiding noise interference and DFE-less
                  fast precharge sampling for over 10Gb/s/pin graphics {DRAM} interface},
  booktitle    = {2013 {IEEE} International Solid-State Circuits Conference - Digest
                  of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
                  17-21, 2013},
  pages        = {312--313},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ISSCC.2013.6487749},
  doi          = {10.1109/ISSCC.2013.6487749},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/SongLLHKCCK13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/LeeKCSPKKCC12,
  author       = {Hyun{-}Woo Lee and
                  Ki{-}Han Kim and
                  Young{-}Kyoung Choi and
                  Ju{-}Hwan Sohn and
                  Nak{-}Kyu Park and
                  Kwan{-}Weon Kim and
                  Chulwoo Kim and
                  Young{-}Jung Choi and
                  Byong{-}Tae Chung},
  title        = {A 1.6 {V} 1.4 Gbp/s/pin Consumer {DRAM} With Self-Dynamic Voltage
                  Scaling Technique in 44 nm {CMOS} Technology},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {47},
  number       = {1},
  pages        = {131--140},
  year         = {2012},
  url          = {https://doi.org/10.1109/JSSC.2011.2164710},
  doi          = {10.1109/JSSC.2011.2164710},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/LeeKCSPKKCC12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/LeeCSKKKKJKPKKCRCKKCC12,
  author       = {Hyun{-}Woo Lee and
                  Hoon Choi and
                  Beom{-}Ju Shin and
                  Kyung{-}Hoon Kim and
                  Kyung Whan Kim and
                  Jaeil Kim and
                  Kwang Hyun Kim and
                  Jongho Jung and
                  Jae{-}Hwan Kim and
                  Eun Young Park and
                  Jong{-}Sam Kim and
                  Jong{-}Hwan Kim and
                  Jin{-}Hee Cho and
                  Nam Gyu Rye and
                  Jun Hyun Chun and
                  Yunsaing Kim and
                  Chulwoo Kim and
                  Young{-}Jung Choi and
                  Byong{-}Tae Chung},
  title        = {A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered {CAS}
                  Latency Controller for {DRAM} Interfaces},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {47},
  number       = {6},
  pages        = {1436--1447},
  year         = {2012},
  url          = {https://doi.org/10.1109/JSSC.2012.2191027},
  doi          = {10.1109/JSSC.2012.2191027},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/LeeCSKKKKJKPKKCRCKKCC12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/KooOKKSLKKLOLLLLJJCKHKCK12,
  author       = {Kibong Koo and
                  Sunghwa Ok and
                  Yonggu Kang and
                  Seungbong Kim and
                  Choungki Song and
                  Hyeyoung Lee and
                  Hyungsoo Kim and
                  Yongmi Kim and
                  Jeonghun Lee and
                  Seunghan Oak and
                  Yosep Lee and
                  Jungyu Lee and
                  Joongho Lee and
                  Hyungyu Lee and
                  Jaemin Jang and
                  Jongho Jung and
                  Byeongchan Choi and
                  Yong{-}Ju Kim and
                  Youngdo Hur and
                  Yunsaing Kim and
                  Byong{-}Tae Chung and
                  Yongtak Kim},
  title        = {A 1.2V 38nm 2.4Gb/s/pin 2Gb {DDR4} {SDRAM} with bank group and {\texttimes}4
                  half-page architecture},
  booktitle    = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2012, San Francisco, CA, USA, February 19-23, 2012},
  pages        = {40--41},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISSCC.2012.6176869},
  doi          = {10.1109/ISSCC.2012.6176869},
  timestamp    = {Mon, 11 Jan 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/KooOKKSLKKLOLLLLJJCKHKCK12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/LeeLSKKKKCPCK12,
  author       = {Hyun{-}Woo Lee and
                  Soo{-}Bin Lim and
                  Junyoung Song and
                  Jabeom Koo and
                  Dae{-}Han Kwon and
                  Jong{-}Ho Kang and
                  Yunsaing Kim and
                  Young{-}Jung Choi and
                  Kunwoo Park and
                  Byong{-}Tae Chung and
                  Chulwoo Kim},
  title        = {A 283.2{\(\mu\)}W 800Mb/s/pin DLL-based data self-aligner for Through-Silicon
                  Via {(TSV)} interface},
  booktitle    = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2012, San Francisco, CA, USA, February 19-23, 2012},
  pages        = {48--50},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISSCC.2012.6176873},
  doi          = {10.1109/ISSCC.2012.6176873},
  timestamp    = {Wed, 17 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/LeeLSKKKKCPCK12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/LeeKCSPKKCC11,
  author       = {Hyun{-}Woo Lee and
                  Ki{-}Han Kim and
                  Young{-}Kyoung Choi and
                  Ju{-}Hwan Shon and
                  Nak{-}Kyu Park and
                  Kwan{-}Weon Kim and
                  Chulwoo Kim and
                  Young{-}Jung Choi and
                  Byong{-}Tae Chung},
  title        = {A 1.6V 1.4Gb/s/pin consumer {DRAM} with self-dynamic voltage-scaling
                  technique in 44nm {CMOS} technology},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
                  Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
                  2011},
  pages        = {502--504},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/ISSCC.2011.5746416},
  doi          = {10.1109/ISSCC.2011.5746416},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/LeeKCSPKKCC11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/MoonC10,
  author       = {Jinyeong Moon and
                  Byong{-}Tae Chung},
  title        = {Sense amplifier with offset mismatch calibration for sub 1-V {DRAM}
                  core operation},
  booktitle    = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
                  30 - June 2, 2010, Paris, France},
  pages        = {3501--3504},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/ISCAS.2010.5537834},
  doi          = {10.1109/ISCAS.2010.5537834},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/MoonC10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/LeeKYPLKKJKRKCKCCK10,
  author       = {Hyun{-}Woo Lee and
                  Yong{-}Hoon Kim and
                  Won{-}Joo Yun and
                  Eun Young Park and
                  Kang Youl Lee and
                  Jaeil Kim and
                  Kwang Hyun Kim and
                  Jongho Jung and
                  Kyung Whan Kim and
                  Nam Gyu Rye and
                  Kwan{-}Weon Kim and
                  Jun Hyun Chun and
                  Chulwoo Kim and
                  Young{-}Jung Choi and
                  Byong{-}Tae Chung and
                  Joong Sik Kih},
  title        = {A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and {OA-DCC}
                  for {DRAM} interface},
  booktitle    = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
                  30 - June 2, 2010, Paris, France},
  pages        = {3861--3864},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/ISCAS.2010.5537703},
  doi          = {10.1109/ISCAS.2010.5537703},
  timestamp    = {Fri, 26 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/LeeKYPLKKJKRKCKCCK10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/socc/ShinCCC10,
  author       = {Dongsuk Shin and
                  Joo{-}Hwan Cho and
                  Young{-}Jung Choi and
                  Byong{-}Tae Chung},
  editor       = {Thomas B{\"{u}}chner and
                  Ramalingam Sridhar and
                  Andrew Marshall and
                  Norbert Schuhmann},
  title        = {Frequency-independent fast-lock register-controlled {DLL} with wide-range
                  duty cycle adjuster},
  booktitle    = {Annual {IEEE} International SoC Conference, SoCC 2010, September 27-29,
                  2010, Las Vegas, NV, USA, Proceedings},
  pages        = {79--82},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/SOCC.2010.5784640},
  doi          = {10.1109/SOCC.2010.5784640},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/socc/ShinCCC10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/LeeYCCLKKYKLLSKCSSMKLPKCAC09,
  author       = {Hyun{-}Woo Lee and
                  Won{-}Joo Yun and
                  Young{-}Kyoung Choi and
                  Hyang{-}Hwa Choi and
                  Jong{-}Jin Lee and
                  Ki{-}Han Kim and
                  Shin{-}Deok Kang and
                  Ji{-}Yeon Yang and
                  Jae{-}Suck Kang and
                  Hyeng{-}Ouk Lee and
                  Dong{-}Uk Lee and
                  Sujeong Sim and
                  Young{-}Ju Kim and
                  Won{-}Jun Choi and
                  Keun{-}Soo Song and
                  Sang{-}Hoon Shin and
                  Hyung{-}Wook Moon and
                  Seung{-}Wook Kwack and
                  Jung{-}Woo Lee and
                  Nak{-}Kyu Park and
                  Kwan{-}Weon Kim and
                  Young{-}Jung Choi and
                  Jin{-}Hong Ahn and
                  Byong{-}Tae Chung},
  title        = {A 1.6V 3.3Gb/s {GDDR3} {DRAM} with dual-mode phase- and delay-locked
                  loop using power-noise management with unregulated power supply in
                  54nm {CMOS}},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
                  Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
                  2009},
  pages        = {140--141},
  publisher    = {{IEEE}},
  year         = {2009},
  url          = {https://doi.org/10.1109/ISSCC.2009.4977347},
  doi          = {10.1109/ISSCC.2009.4977347},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/LeeYCCLKKYKLLSKCSSMKLPKCAC09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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