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ORCIDBibTeX records: Lih-Yih Chiou
@article{DBLP:journals/tvlsi/HuangC21,
author = {Chi{-}Ray Huang and
Lih{-}Yih Chiou},
title = {An Energy-Efficient Conditional Biasing Write Assist With Built-In
Time-Based Write-Margin-Tracking for Low-Voltage {SRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {8},
pages = {1586--1590},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3084041},
doi = {10.1109/TVLSI.2021.3084041},
timestamp = {Thu, 12 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/ChiouHLT21,
author = {Lih{-}Yih Chiou and
Jing{-}Yu Huang and
Chi{-}Kuan Li and
Chen{-}Chung Tsai},
title = {A Reliable Near-Threshold Voltage SRAM-Based {PUF} Utilizing Weight
Detection Technique},
booktitle = {International Symposium on {VLSI} Design, Automation and Test, {VLSI-DAT}
2021, Hsinchu, Taiwan, April 19-22, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-DAT52063.2021.9427315},
doi = {10.1109/VLSI-DAT52063.2021.9427315},
timestamp = {Mon, 17 May 2021 15:11:23 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/ChiouHLT21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aicas/ChiouYSCC19,
author = {Lih{-}Yih Chiou and
Tsung{-}Han Yang and
Jian{-}Tang Syu and
Che{-}Pin Chang and
Yeong{-}Jar Chang},
title = {Intelligent Policy Selection for {GPU} Warp Scheduler},
booktitle = {{IEEE} International Conference on Artificial Intelligence Circuits
and Systems, {AICAS} 2019, Hsinchu, Taiwan, March 18-20, 2019},
pages = {302--303},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/AICAS.2019.8771596},
doi = {10.1109/AICAS.2019.8771596},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aicas/ChiouYSCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChiouWW19,
author = {Lih{-}Yih Chiou and
Chung{-}Han Wu and
Po{-}Cheng Wei},
title = {A Reliable Delay-Based Physical Unclonable Function with Dark-Bit
Avoidance},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702131},
doi = {10.1109/ISCAS.2019.8702131},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChiouWW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChiouYC19,
author = {Lih{-}Yih Chiou and
Chao{-}Kai Yang and
Che{-}Pin Chang},
title = {A Data-Traffic Aware Dynamic Power Management for General-Purpose
Graphics Processing Units},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702405},
doi = {10.1109/ISCAS.2019.8702405},
timestamp = {Sun, 14 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChiouYC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/ChiouHCHL19,
author = {Lih{-}Yih Chiou and
Chi{-}Ray Huang and
Chang{-}Chieh Cheng and
Jing{-}Yu Huang and
Wei{-}Suo Ling},
title = {A Variation-Tolerant Bitline Leakage Sensing Scheme for Near-Threshold
SRAMs},
booktitle = {International Symposium on {VLSI} Design, Automation and Test, {VLSI-DAT}
2019, Hsinchu, Taiwan, April 22-25, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-DAT.2019.8741606},
doi = {10.1109/VLSI-DAT.2019.8741606},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/ChiouHCHL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cds/HuangC18,
author = {Chi{-}Ray Huang and
Lih{-}Yih Chiou},
title = {Single bit-line 8T {SRAM} cell with asynchronous dual word-line control
for bit-interleaved ultra-low voltage operation},
journal = {{IET} Circuits Devices Syst.},
volume = {12},
number = {6},
pages = {713--719},
year = {2018},
url = {https://doi.org/10.1049/iet-cds.2018.5150},
doi = {10.1049/IET-CDS.2018.5150},
timestamp = {Thu, 31 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iet-cds/HuangC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cps/LuHWC18,
author = {Liang{-}Ying Lu and
Tsung{-}Yu Hsieh and
Pei{-}En Weng and
Lih{-}Yih Chiou},
title = {Methodology for developing virtual platforms from power-aware to power-
and thermal-aware at electronic system level},
journal = {{IET} Cyper-Phys. Syst.: Theory {\&} Appl.},
volume = {3},
number = {3},
pages = {150--157},
year = {2018},
url = {https://doi.org/10.1049/iet-cps.2017.0066},
doi = {10.1049/IET-CPS.2017.0066},
timestamp = {Wed, 22 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cps/LuHWC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuC18,
author = {Liang{-}Ying Lu and
Lih{-}Yih Chiou},
title = {Temperature Gradient Exploration Method for Determining the Appropriate
Number of Cells in Mesh-Based Thermal Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3216--3220},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2801225},
doi = {10.1109/TCAD.2018.2801225},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ChienCCHWLS18,
author = {Tsai{-}Kan Chien and
Lih{-}Yih Chiou and
Chi{-}Shian Chang and
Jing{-}Yu Huang and
Chung{-}Han Wu and
Heng{-}Yuan Lee and
Shyh{-}Shyuan Sheu},
title = {Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F\({}^{\mbox{2}}\)/Bit
Nonlinear Sub-Teraohm 0TNR Vertical ReRAM},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {65-II},
number = {9},
pages = {1234--1238},
year = {2018},
url = {https://doi.org/10.1109/TCSII.2017.2778246},
doi = {10.1109/TCSII.2017.2778246},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ChienCCHWLS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HuangWWC18,
author = {Chi{-}Ray Huang and
Kuan{-}Lin Wu and
Chung{-}Han Wu and
Lih{-}Yih Chiou},
title = {Ultra-Low Standby Power {SRAM} with Adaptive Data-Retention-Voltage-Regulating
Scheme},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018,
27-30 May 2018, Florence, Italy},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISCAS.2018.8350944},
doi = {10.1109/ISCAS.2018.8350944},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/HuangWWC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/ChiouCLYCL18,
author = {Lih{-}Yih Chiou and
Chun{-}Hao Chang and
Liang{-}Ying Lu and
Wei{-}Hsuan Yang and
Yeong{-}Jar Chang and
Juin{-}Ming Lu},
title = {Fast Steady-State Thermal Analysis},
booktitle = {International SoC Design Conference, {ISOCC} 2018, Daegu, South Korea,
November 12-15, 2018},
pages = {15--16},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISOCC.2018.8649912},
doi = {10.1109/ISOCC.2018.8649912},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isocc/ChiouCLYCL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/LuC17,
author = {Liang{-}Ying Lu and
Lih{-}Yih Chiou},
title = {Temperature gradient-aware thermal simulator for three-dimensional
integrated circuits},
journal = {{IET} Comput. Digit. Tech.},
volume = {11},
number = {5},
pages = {190--196},
year = {2017},
url = {https://doi.org/10.1049/iet-cdt.2016.0149},
doi = {10.1049/IET-CDT.2016.0149},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/LuC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/CruzHLCL17,
author = {Hugo Cruz and
Hong{-}Yi Huang and
Ching{-}Hsing Luo and
Lih{-}Yih Chiou and
Shuenn{-}Yuh Lee},
title = {A novel clock-pulse-width calibration technique for charge redistribution
DACs},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,
Baltimore, MD, USA, May 28-31, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISCAS.2017.8050483},
doi = {10.1109/ISCAS.2017.8050483},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/CruzHLCL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ChienCTSWTW17,
author = {Tsai{-}Kan Chien and
Lih{-}Yih Chiou and
Yi{-}Sung Tsou and
Shyh{-}Shyuan Sheu and
Pei{-}Hua Wang and
Ming{-}Jinn Tsai and
Chih{-}I Wu},
title = {Write-energy-saving ReRAM-based nonvolatile {SRAM} with redundant
bit-write-aware controller for last-level caches},
booktitle = {2017 {IEEE/ACM} International Symposium on Low Power Electronics and
Design, {ISLPED} 2017, Taipei, Taiwan, July 24-26, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISLPED.2017.8009153},
doi = {10.1109/ISLPED.2017.8009153},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/islped/ChienCTSWTW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/ChienCSLLKTW16,
author = {Tsai{-}Kan Chien and
Lih{-}Yih Chiou and
Shyh{-}Shyuan Sheu and
Jing{-}Cian Lin and
Chang{-}Chia Lee and
Tzu{-}Kun Ku and
Ming{-}Jinn Tsai and
Chih{-}I Wu},
title = {Low-Power {MCU} With Embedded ReRAM Buffers as Sensor Hub for IoT
Applications},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {6},
number = {2},
pages = {247--257},
year = {2016},
url = {https://doi.org/10.1109/JETCAS.2016.2547778},
doi = {10.1109/JETCAS.2016.2547778},
timestamp = {Tue, 06 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esticas/ChienCSLLKTW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/ChienCCSWTW16,
author = {Tsai{-}Kan Chien and
Lih{-}Yih Chiou and
Chieh{-}Wen Cheng and
Shyh{-}Shyuan Sheu and
Pei{-}Hua Wang and
Ming{-}Jinn Tsai and
Chih{-}I Wu},
title = {Memory access algorithm for low energy {CPU/GPU} heterogeneous systems
with hybrid {DRAM/NVM} memory architecture},
booktitle = {2016 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
2016, Jeju, South Korea, October 25-28, 2016},
pages = {461--464},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/APCCAS.2016.7804003},
doi = {10.1109/APCCAS.2016.7804003},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/apccas/ChienCCSWTW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LuCCYLCTLCCTCL16,
author = {Liang{-}Ying Lu and
Ching{-}Yao Chang and
Zhao{-}Hong Chen and
Bo{-}Ting Yeh and
Tai{-}Hua Lu and
Peng{-}Yu Chen and
Pin{-}Hao Tang and
Kuen{-}Jong Lee and
Lih{-}Yih Chiou and
Soon{-}Jyh Chang and
Chien{-}Hung Tsai and
Chung{-}Ho Chen and
Jai{-}Ming Lin},
title = {A testable and debuggable dual-core system with thermal-aware dynamic
voltage and frequency scaling},
booktitle = {21st Asia and South Pacific Design Automation Conference, {ASP-DAC}
2016, Macao, Macao, January 25-28, 2016},
pages = {17--18},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASPDAC.2016.7427980},
doi = {10.1109/ASPDAC.2016.7427980},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LuCCYLCTLCCTCL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChienCCSLWKTW16,
author = {Tsai{-}Kan Chien and
Lih{-}Yih Chiou and
Yao{-}Chun Chuang and
Shyh{-}Shyuan Sheu and
Heng{-}Yuan Li and
Pei{-}Hua Wang and
Tzu{-}Kun Ku and
Ming{-}Jinn Tsai and
Chih{-}I Wu},
title = {A low store energy and robust ReRAM-based flip-flop for normally off
microprocessors},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016,
Montr{\'{e}}al, QC, Canada, May 22-25, 2016},
pages = {2803--2806},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISCAS.2016.7539175},
doi = {10.1109/ISCAS.2016.7539175},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChienCCSLWKTW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/ChiouLL15,
author = {Lih{-}Yih Chiou and
Liang{-}Ying Lu and
Chieh{-}Yu Lin},
title = {An effective matrix compression method for GPU-accelerated thermal
analysis},
booktitle = {{VLSI} Design, Automation and Test, {VLSI-DAT} 2015, Hsinchu, Taiwan,
April 27-29, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-DAT.2015.7114505},
doi = {10.1109/VLSI-DAT.2015.7114505},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/ChiouLL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChiouHW14,
author = {Lih{-}Yih Chiou and
Chi{-}Ray Huang and
Ming{-}Hung Wu},
title = {A power-efficient pulse-based in-situ timing error predictor for PVT-variation
sensitive circuits},
booktitle = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
Melbourne, Victoria, Australia, June 1-5, 2014},
pages = {1215--1218},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISCAS.2014.6865360},
doi = {10.1109/ISCAS.2014.6865360},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChiouHW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/LuoHC14,
author = {Shien{-}Chun Luo and
Chi{-}Ray Huang and
Lih{-}Yih Chiou},
title = {An ultra-low-power adaptive-body-bias control for subthreshold circuits},
booktitle = {Technical Papers of 2014 International Symposium on {VLSI} Design,
Automation and Test, {VLSI-DAT} 2014, Hsinchu, Taiwan, April 28-30,
2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-DAT.2014.6834901},
doi = {10.1109/VLSI-DAT.2014.6834901},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/LuoHC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/ChiouLLS12,
author = {Lih{-}Yih Chiou and
Liang{-}Ying Lu and
Bo{-}Chi Lin and
Alan P. Su},
title = {Buffer size minimization method considering mix-clock domains and
discontinuous data access},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2012,
Kaohsiung, Taiwan, December 2-5, 2012},
pages = {380--383},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/APCCAS.2012.6419051},
doi = {10.1109/APCCAS.2012.6419051},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/apccas/ChiouLLS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LuoHC12,
author = {Shien{-}Chun Luo and
Chi{-}Ray Huang and
Lih{-}Yih Chiou},
title = {Minimum convertible voltage analysis for ratioless and robust subthreshold
level conversion},
booktitle = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2012, Seoul, Korea (South), May 20-23, 2012},
pages = {2553--2556},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCAS.2012.6271824},
doi = {10.1109/ISCAS.2012.6271824},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LuoHC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChenCC11,
author = {Yi{-}Siou Chen and
Lih{-}Yih Chiou and
Hsun{-}Hsiang Chang},
title = {A fast and effective dynamic trace-based method for analyzing architectural
performance},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {591--596},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722258},
doi = {10.1109/ASPDAC.2011.5722258},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ChenCC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/LuoC10,
author = {Shien{-}Chun Luo and
Lih{-}Yih Chiou},
title = {A Sub-200-mV Voltage-Scalable {SRAM} With Tolerance of Access Failure
by Self-Activated Bitline Sensing},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {57-II},
number = {6},
pages = {440--445},
year = {2010},
url = {https://doi.org/10.1109/TCSII.2010.2048360},
doi = {10.1109/TCSII.2010.2048360},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/LuoC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/WangMCCPJR10,
author = {Yongtao Wang and
Hamid Mahmoodi and
Lih{-}Yih Chiou and
Hunsoo Choo and
Jongsun Park and
Woopyo Jeong and
Kaushik Roy},
title = {Energy-efficient Hardware Architecture and {VLSI} Implementation of
a Polyphase Channelizer with Applications to Subband Adaptive Filtering},
journal = {J. Signal Process. Syst.},
volume = {58},
number = {2},
pages = {125--137},
year = {2010},
url = {https://doi.org/10.1007/s11265-008-0323-2},
doi = {10.1007/S11265-008-0323-2},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/WangMCCPJR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChiouCL09,
author = {Lih{-}Yih Chiou and
Yi{-}Siou Chen and
Chih{-}Hsien Lee},
title = {System-Level Bus-Based Communication Architecture Exploration Using
a Pseudoparallel Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {8},
pages = {1213--1223},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2021733},
doi = {10.1109/TCAD.2009.2021733},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChiouCL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChiouL09,
author = {Lih{-}Yih Chiou and
Shien{-}Chun Luo},
title = {Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With
Symmetry in Setup Times and Insensitivity to Output Parasitics},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {17},
number = {11},
pages = {1659--1663},
year = {2009},
url = {https://doi.org/10.1109/TVLSI.2008.2007959},
doi = {10.1109/TVLSI.2008.2007959},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChiouL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChiouL07,
author = {Lih{-}Yih Chiou and
Shien{-}Chun Luo},
title = {An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {1157--1160},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378255},
doi = {10.1109/ISCAS.2007.378255},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChiouL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangCW06,
author = {Meng{-}Fan Chang and
Lih{-}Yih Chiou and
Kuei{-}Ann Wen},
title = {A full code-patterns coverage high-speed embedded {ROM} using dynamic
virtual guardian technique},
journal = {{IEEE} J. Solid State Circuits},
volume = {41},
number = {2},
pages = {496--506},
year = {2006},
url = {https://doi.org/10.1109/JSSC.2005.862343},
doi = {10.1109/JSSC.2005.862343},
timestamp = {Fri, 15 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChangCW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ChangCW06,
author = {Meng{-}Fan Chang and
Lih{-}Yih Chiou and
Kuei{-}Ann Wen},
title = {Crosstalk-insensitive via-programming ROMs using content-aware design
framework},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {53-II},
number = {6},
pages = {443--447},
year = {2006},
url = {https://doi.org/10.1109/TCSII.2006.873640},
doi = {10.1109/TCSII.2006.873640},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ChangCW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiuCC06,
author = {Yen{-}Ting Liu and
Lih{-}Yih Chiou and
Soon{-}Jyh Chang},
title = {Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1693587},
doi = {10.1109/ISCAS.2006.1693587},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LiuCC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/ChiouBR05,
author = {Lih{-}Yih Chiou and
Swarup Bhunia and
Kaushik Roy},
title = {Synthesis of application-specific highly efficient multi-mode cores
for embedded systems},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {4},
number = {1},
pages = {168--188},
year = {2005},
url = {https://doi.org/10.1145/1053271.1053278},
doi = {10.1145/1053271.1053278},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/ChiouBR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icassp/WangMCCPJR04,
author = {Yongtao Wang and
Hamid Mahmoodi and
Lih{-}Yih Chiou and
Hunsoo Choo and
Jongsun Park and
Woopyo Jeong and
Kaushik Roy},
title = {Hardware architecture and {VLSI} implementation of a low-power high-performance
polyphase channelizer with applications to subband adaptive filtering},
booktitle = {2004 {IEEE} International Conference on Acoustics, Speech, and Signal
Processing, {ICASSP} 2004, Montreal, Quebec, Canada, May 17-21, 2004},
pages = {97--100},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/ICASSP.2004.1327056},
doi = {10.1109/ICASSP.2004.1327056},
timestamp = {Mon, 22 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icassp/WangMCCPJR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChiouBR03,
author = {Lih{-}Yih Chiou and
Swarup Bhunia and
Kaushik Roy},
title = {Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems
for Low-Power Applications},
booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2003), 3-7 March 2003, Munich, Germany},
pages = {10096--10103},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10145},
doi = {10.1109/DATE.2003.10145},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/ChiouBR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JohnsonSCR02,
author = {Mark C. Johnson and
Dinesh Somasekhar and
Lih{-}Yih Chiou and
Kaushik Roy},
title = {Leakage control with efficient use of transistor stacks in single
threshold {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {1},
pages = {1--5},
year = {2002},
url = {https://doi.org/10.1109/92.988724},
doi = {10.1109/92.988724},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JohnsonSCR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ChiouMR01,
author = {Lih{-}Yih Chiou and
Khurram Muhammad and
Kaushik Roy},
title = {Signal Strength Based Switching Activity Modeling and Estimation for
{DSP} Applications},
journal = {{VLSI} Design},
volume = {12},
number = {2},
pages = {233--243},
year = {2001},
url = {https://doi.org/10.1155/2001/35832},
doi = {10.1155/2001/35832},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/ChiouMR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icassp/ChiouMR01,
author = {Lih{-}Yih Chiou and
Khurram Muhammad and
Kaushik Roy},
title = {{DSP} data path synthesis for low-power applications},
booktitle = {{IEEE} International Conference on Acoustics, Speech, and Signal Processing,
{ICASSP} 2001, 7-11 May, 2001, Salt Palace Convention Center, Salt
Lake City, Utah, USA, Proceedings},
pages = {1165--1168},
publisher = {{IEEE}},
year = {2001},
url = {https://doi.org/10.1109/ICASSP.2001.941130},
doi = {10.1109/ICASSP.2001.941130},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icassp/ChiouMR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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