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ORCIDBibTeX records: Gautham N. Chinya
@inproceedings{DBLP:conf/vlsid/RahaKMVMSBC21,
author = {Arnab Raha and
Sang Kyun Kim and
Deepak Mathaikutty and
Guruguhanathan Venkataramanan and
Debabrata Mohapatra and
Raymond Sung and
Cormac Brick and
Gautham N. Chinya},
title = {Design Considerations for Edge Neural Network Accelerators: An Industry
Perspective},
booktitle = {34th International Conference on {VLSI} Design and 20th International
Conference on Embedded Systems, {VLSID} 2021, Guwahati, India, February
20-24, 2021},
pages = {328--333},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSID51830.2021.00061},
doi = {10.1109/VLSID51830.2021.00061},
timestamp = {Mon, 14 Nov 2022 15:28:08 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/RahaKMVMSBC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2009-00202,
author = {Karthik Sankaranarayanan and
Chit{-}Kwan Lin and
Gautham N. Chinya},
title = {Helper Without Threads: Customized Prefetching for Delinquent Irregular
Loads},
journal = {CoRR},
volume = {abs/2009.00202},
year = {2020},
url = {https://arxiv.org/abs/2009.00202},
eprinttype = {arXiv},
eprint = {2009.00202},
timestamp = {Wed, 16 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2009-00202.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/MeinerzhagenTMV19,
author = {Pascal Andreas Meinerzhagen and
Carlos Tokunaga and
Andres Malavasi and
Vaibhav A. Vaidya and
Ashwin Mendon and
Deepak Mathaikutty and
Jaydeep Kulkarni and
Charles Augustine and
Minki Cho and
Stephen T. Kim and
George E. Matthew and
Rinkle Jain and
Joseph F. Ryan and
Chung{-}Ching Peng and
Somnath Paul and
Sriram R. Vangal and
Brando Perez Esparza and
Luis Cuellar and
Michael Woodman and
Bala Iyer and
Subramaniam Maiyuran and
Gautham N. Chinya and
Xiang Zou and
Yuyun Liao and
Krishnan Ravichandran and
Hong Wang and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {An Energy-Efficient Graphics Processor in 14-nm Tri-Gate {CMOS} Featuring
Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep,
and {\textdollar}\{V\}{\_}\{{\textbackslash}text\{MIN\}\}{\textdollar}
Optimization},
journal = {{IEEE} J. Solid State Circuits},
volume = {54},
number = {1},
pages = {144--157},
year = {2019},
url = {https://doi.org/10.1109/JSSC.2018.2875097},
doi = {10.1109/JSSC.2018.2875097},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/MeinerzhagenTMV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/TarsaCSCGSLCSW19,
author = {Stephen J. Tarsa and
Rangeen Basu Roy Chowdhury and
Julien Sebot and
Gautham N. Chinya and
Jayesh Gaur and
Karthik Sankaranarayanan and
Chit{-}Kwan Lin and
Robert Chappell and
Ronak Singhal and
Hong Wang},
editor = {Srilatha Bobbie Manne and
Hillery C. Hunter and
Erik R. Altman},
title = {Post-silicon {CPU} adaptation made practical using machine learning},
booktitle = {Proceedings of the 46th International Symposium on Computer Architecture,
{ISCA} 2019, Phoenix, AZ, USA, June 22-26, 2019},
pages = {14--26},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3307650.3322267},
doi = {10.1145/3307650.3322267},
timestamp = {Fri, 09 Jul 2021 15:51:20 +0200},
biburl = {https://dblp.org/rec/conf/isca/TarsaCSCGSLCSW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1906-09889,
author = {Stephen J. Tarsa and
Chit{-}Kwan Lin and
Gokce Keskin and
Gautham N. Chinya and
Hong Wang},
title = {Improving Branch Prediction By Modeling Global History with Convolutional
Neural Networks},
journal = {CoRR},
volume = {abs/1906.09889},
year = {2019},
url = {http://arxiv.org/abs/1906.09889},
eprinttype = {arXiv},
eprint = {1906.09889},
timestamp = {Thu, 27 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1906-09889.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computer/LinWCCDLW18,
author = {Chit{-}Kwan Lin and
Andreas Wild and
Gautham N. Chinya and
Yongqiang Cao and
Mike Davies and
Daniel M. Lavery and
Hong Wang},
title = {Programming Spiking Neural Networks on Intel's Loihi},
journal = {Computer},
volume = {51},
number = {3},
pages = {52--61},
year = {2018},
url = {https://doi.org/10.1109/MC.2018.157113521},
doi = {10.1109/MC.2018.157113521},
timestamp = {Wed, 12 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computer/LinWCCDLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/DaviesSLCCCDJIJ18,
author = {Mike Davies and
Narayan Srinivasa and
Tsung{-}Han Lin and
Gautham N. Chinya and
Yongqiang Cao and
Sri Harsha Choday and
Georgios D. Dimou and
Prasad Joshi and
Nabil Imam and
Shweta Jain and
Yuyun Liao and
Chit{-}Kwan Lin and
Andrew Lines and
Ruokun Liu and
Deepak Mathaikutty and
Steven McCoy and
Arnab Paul and
Jonathan Tse and
Guruguhanathan Venkataramanan and
Yi{-}Hsin Weng and
Andreas Wild and
Yoonseok Yang and
Hong Wang},
title = {Loihi: {A} Neuromorphic Manycore Processor with On-Chip Learning},
journal = {{IEEE} Micro},
volume = {38},
number = {1},
pages = {82--99},
year = {2018},
url = {https://doi.org/10.1109/MM.2018.112130359},
doi = {10.1109/MM.2018.112130359},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/DaviesSLCCCDJIJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/MeinerzhagenTMV18,
author = {Pascal Meinerzhagen and
Carlos Tokunaga and
Andres Malavasi and
Vaibhav A. Vaidya and
Ashwin Mendon and
Deepak Mathaikutty and
Jaydeep Kulkarni and
Charles Augustine and
Minki Cho and
Stephen T. Kim and
George E. Matthew and
Rinkle Jain and
Joseph F. Ryan and
Chung{-}Ching Peng and
Somnath Paul and
Sriram R. Vangal and
Brando Perez Esparza and
Luis Cuellar and
Michael Woodman and
Bala Iyer and
Subramaniam Maiyuran and
Gautham N. Chinya and
Chris Zou and
Yuyun Liao and
Krishnan Ravichandran and
Hong Wang and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {An energy-efficient graphics processor featuring fine-grain {DVFS}
with integrated voltage regulators, execution-unit turbo, and retentive
sleep in 14nm tri-gate {CMOS}},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {38--40},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310172},
doi = {10.1109/ISSCC.2018.8310172},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/MeinerzhagenTMV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pldi/LinWCLDW18,
author = {Chit{-}Kwan Lin and
Andreas Wild and
Gautham N. Chinya and
Tsung{-}Han Lin and
Mike Davies and
Hong Wang},
editor = {Jeffrey S. Foster and
Dan Grossman},
title = {Mapping spiking neural networks onto a manycore neuromorphic architecture},
booktitle = {Proceedings of the 39th {ACM} {SIGPLAN} Conference on Programming
Language Design and Implementation, {PLDI} 2018, Philadelphia, PA,
USA, June 18-22, 2018},
pages = {78--89},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3192366.3192371},
doi = {10.1145/3192366.3192371},
timestamp = {Wed, 23 Jun 2021 15:34:31 +0200},
biburl = {https://dblp.org/rec/conf/pldi/LinWCLDW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigops/ChinyaCWJLPW11,
author = {Gautham N. Chinya and
Jamison D. Collins and
Perry H. Wang and
Hong Jiang and
Guei{-}Yuan Lueh and
Thomas Piazza and
Hong Wang},
title = {Bothnia: a dual-personality extension to the Intel integrated graphics
driver},
journal = {{ACM} {SIGOPS} Oper. Syst. Rev.},
volume = {45},
number = {1},
pages = {11--20},
year = {2011},
url = {https://doi.org/10.1145/1945023.1945027},
doi = {10.1145/1945023.1945027},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigops/ChinyaCWJLPW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cf/OttoniCHCKSDSW11,
author = {Guilherme Ottoni and
Gautham N. Chinya and
Gerolf Hoflehner and
Jamison D. Collins and
Amit Kumar and
Ethan Schuchman and
David R. Ditzel and
Ronak Singhal and
Hong Wang},
editor = {Calin Cascaval and
Pedro Trancoso and
Viktor K. Prasanna},
title = {AstroLIT: enabling simulation-based microarchitecture comparison between
Intel{\textregistered} and Transmeta designs},
booktitle = {Proceedings of the 8th Conference on Computing Frontiers, 2011, Ischia,
Italy, May 3-5, 2011},
pages = {21},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/2016604.2016629},
doi = {10.1145/2016604.2016629},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cf/OttoniCHCKSDSW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SchelleCSWZCPMOHSBSW10,
author = {Graham Schelle and
Jamison D. Collins and
Ethan Schuchman and
Perry H. Wang and
Xiang Zou and
Gautham N. Chinya and
Ralf Plate and
Thorsten Mattner and
Franz Olbrich and
Per Hammarlund and
Ronak Singhal and
Jim Brayton and
Sebastian Steibl and
Hong Wang},
editor = {Peter Y. K. Cheung and
John Wawrzynek},
title = {Intel nehalem processor core made {FPGA} synthesizable},
booktitle = {Proceedings of the {ACM/SIGDA} 18th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2010, Monterey, California, USA,
February 21-23, 2010},
pages = {3--12},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1723112.1723116},
doi = {10.1145/1723112.1723116},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/SchelleCSWZCPMOHSBSW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WangCWKSCSSDSW09,
author = {Perry H. Wang and
Jamison D. Collins and
Christopher T. Weaver and
Belliappa Kuttanna and
Shahram Salamian and
Gautham N. Chinya and
Ethan Schuchman and
Oliver Schilling and
Thorsten Doil and
Sebastian Steibl and
Hong Wang},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Intel{\textregistered} atom\({}^{\mbox{TM}}\) processor core made
FPGA-synthesizable},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {209--218},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508160},
doi = {10.1145/1508128.1508160},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/WangCWKSCSSDSW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEpact/WongBSACWCGJW08,
author = {Henry Wong and
Anne Bracy and
Ethan Schuchman and
Tor M. Aamodt and
Jamison D. Collins and
Perry H. Wang and
Gautham N. Chinya and
Ankur Khandelwal Groen and
Hong Jiang and
Hong Wang},
editor = {Andreas Moshovos and
David Tarditi and
Kunle Olukotun},
title = {Pangaea: a tightly-coupled {IA32} heterogeneous chip multiprocessor},
booktitle = {17th International Conference on Parallel Architectures and Compilation
Techniques, {PACT} 2008, Toronto, Ontario, Canada, October 25-29,
2008},
pages = {52--61},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1454115.1454125},
doi = {10.1145/1454115.1454125},
timestamp = {Wed, 11 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/IEEEpact/WongBSACWCGJW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ics/WangCCLMYW07,
author = {Perry H. Wang and
Jamison D. Collins and
Gautham N. Chinya and
Bernard Lint and
Asit Mallick and
Koichi Yamada and
Hong Wang},
editor = {Burton J. Smith},
title = {Sequencer virtualization},
booktitle = {Proceedings of the 21th Annual International Conference on Supercomputing,
{ICS} 2007, Seattle, Washington, USA, June 17-21, 2007},
pages = {148--157},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1274971.1274993},
doi = {10.1145/1274971.1274993},
timestamp = {Tue, 06 Nov 2018 11:07:02 +0100},
biburl = {https://dblp.org/rec/conf/ics/WangCCLMYW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pldi/WangCCJTGYLW07,
author = {Perry H. Wang and
Jamison D. Collins and
Gautham N. Chinya and
Hong Jiang and
Xinmin Tian and
Milind Girkar and
Nick Y. Yang and
Guei{-}Yuan Lueh and
Hong Wang},
editor = {Jeanne Ferrante and
Kathryn S. McKinley},
title = {{EXOCHI:} architecture and programming environment for a heterogeneous
multi-core multithreaded system},
booktitle = {Proceedings of the {ACM} {SIGPLAN} 2007 Conference on Programming
Language Design and Implementation, San Diego, California, USA, June
10-13, 2007},
pages = {156--166},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1250734.1250753},
doi = {10.1145/1250734.1250753},
timestamp = {Fri, 25 Jun 2021 14:48:54 +0200},
biburl = {https://dblp.org/rec/conf/pldi/WangCCJTGYLW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/HankinsCCWRWS06,
author = {Richard A. Hankins and
Gautham N. Chinya and
Jamison D. Collins and
Perry H. Wang and
Ryan N. Rakvic and
Hong Wang and
John Paul Shen},
title = {Multiple Instruction Stream Processor},
booktitle = {33rd International Symposium on Computer Architecture {(ISCA} 2006),
June 17-21, 2006, Boston, MA, {USA}},
pages = {114--127},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISCA.2006.29},
doi = {10.1109/ISCA.2006.29},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/HankinsCCWRWS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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