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ORCIDBibTeX records: Yu-Guang Chen
@article{DBLP:journals/tcad/ChenWLCS24,
author = {Yu{-}Guang Chen and
Chieh{-}Shih Wang and
Ing{-}Chao Lin and
Zheng{-}Wei Chen and
Ulf Schlichtmann},
title = {Aging-Aware Energy-Efficient Task Deployment of Heterogeneous Multicore
Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {43},
number = {5},
pages = {1580--1593},
year = {2024},
url = {https://doi.org/10.1109/TCAD.2023.3323163},
doi = {10.1109/TCAD.2023.3323163},
timestamp = {Sun, 05 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenWLCS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HungCLYTC23,
author = {Wei{-}Tse Hung and
Yu{-}Guang Chen and
Jhen{-}Gang Lin and
Yun{-}Wei Yang and
Cheng{-}Hong Tsai and
Mango Chia{-}Tso Chao},
title = {{DRC} Violation Prediction After Global Route Through Convolutional
Neural Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1425--1438},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3271932},
doi = {10.1109/TVLSI.2023.3271932},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HungCLYTC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apsipa/ZhuoCC23,
author = {Yin{-}Rong Zhuo and
Hui{-}Lin Chen and
Yu{-}Guang Chen},
title = {{DOC:} {A} Novel DOuble-Contour-Based Macro Placement Framework for
Mixed-Size Designs},
booktitle = {Asia Pacific Signal and Information Processing Association Annual
Summit and Conference, {APSIPA} {ASC} 2023, Taipei, Taiwan, October
31 - Nov. 3, 2023},
pages = {1392--1397},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/APSIPAASC58517.2023.10317276},
doi = {10.1109/APSIPAASC58517.2023.10317276},
timestamp = {Sat, 02 Dec 2023 14:05:45 +0100},
biburl = {https://dblp.org/rec/conf/apsipa/ZhuoCC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChenHL23,
author = {Yu{-}Guang Chen and
Po{-}Yeh Huang and
Jin{-}Fu Li},
editor = {Atsushi Takahashi},
title = {An On-Line Aging Detection and Tolerance Framework for Improving Reliability
of STT-MRAMs},
booktitle = {Proceedings of the 28th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2023, Tokyo, Japan, January 16-19, 2023},
pages = {13--18},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3566097.3567908},
doi = {10.1145/3566097.3567908},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ChenHL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/ChenT23,
author = {Yu{-}Guang Chen and
Ying{-}Jing Tsai},
editor = {Luca Cassano and
Mihalis Psarakis and
Marcello Traiola and
Alberto Bosio},
title = {Reliability of Computing-In-Memories: Threats, Detection Methods,
and Mitigation Approaches},
booktitle = {{IEEE} International Symposium on Defect and Fault Tolerance in {VLSI}
and Nanotechnology Systems, {DFT} 2023, Juan-Les-Pins, France, October
3-5, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/DFT59622.2023.10313545},
doi = {10.1109/DFT59622.2023.10313545},
timestamp = {Tue, 21 Nov 2023 12:38:06 +0100},
biburl = {https://dblp.org/rec/conf/dft/ChenT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LinCYHTFC23,
author = {Jhen{-}Gang Lin and
Yu{-}Guang Chen and
Yun{-}Wei Yang and
Wei{-}Tse Hung and
Cheng{-}Hong Tsai and
De{-}Shiun Fu and
Mango Chia{-}Tso Chao},
editor = {Himanshu Thapliyal and
Ronald F. DeMara and
Inna Partin{-}Vaisband and
Srinivas Katkoori},
title = {{DRC} Violation Prediction with Pre-global-routing Features Through
Convolutional Neural Network},
booktitle = {Proceedings of the Great Lakes Symposium on {VLSI} 2023, {GLSVLSI}
2023, Knoxville, TN, USA, June 5-7, 2023},
pages = {313--319},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3583781.3590216},
doi = {10.1145/3583781.3590216},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/LinCYHTFC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SatoWCH23,
author = {Takashi Sato and
Chun{-}Yao Wang and
Yu{-}Guang Chen and
Tsung{-}Wei Huang},
title = {Invited Paper: Overview of 2023 {CAD} Contest at {ICCAD}},
booktitle = {{IEEE/ACM} International Conference on Computer Aided Design, {ICCAD}
2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICCAD57390.2023.10323648},
doi = {10.1109/ICCAD57390.2023.10323648},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/SatoWCH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aicas/ChenHHJ22,
author = {Yu{-}Guang Chen and
Tsung{-}Han Hsieh and
Yi{-}Chen Ho and
Jing{-}Yang Jou},
title = {A Novel {DNN} Accelerator for Light-weight Neural Networks: Concept
and Design},
booktitle = {4th {IEEE} International Conference on Artificial Intelligence Circuits
and Systems, {AICAS} 2022, Incheon, Republic of Korea, June 13-15,
2022},
pages = {250--253},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/AICAS54282.2022.9869919},
doi = {10.1109/AICAS54282.2022.9869919},
timestamp = {Fri, 16 Sep 2022 20:28:36 +0200},
biburl = {https://dblp.org/rec/conf/aicas/ChenHHJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChenWHS22,
author = {Yu{-}Guang Chen and
Chun{-}Yao Wang and
Tsung{-}Wei Huang and
Takashi Sato},
editor = {Tulika Mitra and
Evangeline F. Y. Young and
Jinjun Xiong},
title = {Overview of 2022 {CAD} Contest at {ICCAD}},
booktitle = {Proceedings of the 41st {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2022, San Diego, California, USA, 30 October 2022
- 3 November 2022},
pages = {92:1--92:3},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3508352.3561106},
doi = {10.1145/3508352.3561106},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/ChenWHS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/ChenWL22,
author = {Yu{-}Guang Chen and
Chi{-}Hsu Wang and
Ing{-}Chao Lin},
title = {An Aging Detection and Tolerance Framework for 8T {SRAM} Dot Product
{CIM} Engine},
booktitle = {19th International SoC Design Conference, {ISOCC} 2022, Gangneung-si,
Republic of Korea, October 19-22, 2022},
pages = {161--162},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISOCC56007.2022.10031538},
doi = {10.1109/ISOCC56007.2022.10031538},
timestamp = {Wed, 15 Feb 2023 22:08:05 +0100},
biburl = {https://dblp.org/rec/conf/isocc/ChenWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenLCL21,
author = {Yu{-}Guang Chen and
Ing{-}Chao Lin and
Kun{-}Wei Chiu and
Cheng{-}Hsuan Liu},
title = {An efficient \emph{NBTI}-aware wake-up strategy: Concept, design,
and manipulation},
journal = {Integr.},
volume = {80},
pages = {60--71},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.04.003},
doi = {10.1016/J.VLSI.2021.04.003},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChenLCL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/ChangCHL21,
author = {Wei Chang and
Yu{-}Guang Chen and
Po{-}Yeh Huang and
Jin{-}Fu Li},
editor = {Luigi Dilillo and
Luca Cassano and
Athanasios Papadimitriou},
title = {An Aging-Aware {CMOS} {SRAM} Structure Design for Boolean Logic In-Memory
Computing},
booktitle = {36th {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} and Nanotechnology Systems, {DFT} 2021, Athens, Greece,
October 6-8, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DFT52944.2021.9568343},
doi = {10.1109/DFT52944.2021.9568343},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dft/ChangCHL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HuangCWS21,
author = {Tsung{-}Wei Huang and
Yu{-}Guang Chen and
Chun{-}Yao Wang and
Takashi Sato},
title = {Overview of 2021 {CAD} Contest at {ICCAD}},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2021, Munich, Germany, November 1-4, 2021},
pages = {1--3},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCAD51958.2021.9643523},
doi = {10.1109/ICCAD51958.2021.9643523},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/HuangCWS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/ChenCHHJ21,
author = {Yu{-}Guang Chen and
Hung{-}Yi Chiang and
Chi{-}Wei Hsu and
Tsung{-}Han Hsieh and
Jing{-}Yang Jou},
title = {A Reconfigurable Accelerator Design for Quantized Depthwise Separable
Convolutions},
booktitle = {18th International SoC Design Conference, {ISOCC} 2021, Jeju Island,
South Korea, Republic of, October 6-9, 2021},
pages = {290--291},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISOCC53507.2021.9613976},
doi = {10.1109/ISOCC53507.2021.9613976},
timestamp = {Mon, 06 Dec 2021 17:33:24 +0100},
biburl = {https://dblp.org/rec/conf/isocc/ChenCHHJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ChenLW21,
author = {Yu{-}Guang Chen and
Ing{-}Chao Lin and
Yong{-}Che Wei},
title = {A Novel NBTI-Aware Chip Remaining Lifetime Prediction Framework Using
Machine Learning},
booktitle = {22nd International Symposium on Quality Electronic Design, {ISQED}
2021, Santa Clara, CA, USA, April 7-9, 2021},
pages = {476--481},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISQED51717.2021.9424356},
doi = {10.1109/ISQED51717.2021.9424356},
timestamp = {Mon, 17 May 2021 16:05:56 +0200},
biburl = {https://dblp.org/rec/conf/isqed/ChenLW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/ChenHCHJ21,
author = {Yu{-}Guang Chen and
Chi{-}Wei Hsu and
Hung{-}Yi Chiang and
Tsung{-}Han Hsieh and
Jing{-}Yang Jou},
editor = {Gang Qu and
Jinjun Xiong and
Danella Zhao and
Venki Muthukumar and
Md Farhadur Reza and
Ramalingam Sridhar},
title = {A Hierarchical and Reconfigurable Process Element Design for Quantized
Neural Networks},
booktitle = {34th {IEEE} International System-on-Chip Conference, {SOCC} 2021,
Las Vegas, NV, USA, September 14-17, 2021},
pages = {278--283},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SOCC52499.2021.9739487},
doi = {10.1109/SOCC52499.2021.9739487},
timestamp = {Wed, 30 Mar 2022 11:02:31 +0200},
biburl = {https://dblp.org/rec/conf/socc/ChenHCHJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChangLCC20,
author = {Wen{-}Hsiang Chang and
Li{-}Yi Lin and
Yu{-}Guang Chen and
Mango C.{-}T. Chao},
title = {Power Distribution Network Generation for Optimizing IR-Drop Aware
Timing},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2020, San Diego, CA, USA, November 2-5, 2020},
pages = {146:1--146:9},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1145/3400302.3415628},
doi = {10.1145/3400302.3415628},
timestamp = {Mon, 18 Jan 2021 09:56:56 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ChangLCC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icce-tw/Chen20,
author = {Yu{-}Guang Chen},
title = {An Artificial Neuron Network Based Chip Health Assessment Framework
for {IC} Recycling},
booktitle = {{IEEE} International Conference on Consumer Electronics - Taiwan,
{ICCE-TW} 2020, Taoyuan, Taiwan, September 28-30, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICCE-Taiwan49838.2020.9258117},
doi = {10.1109/ICCE-TAIWAN49838.2020.9258117},
timestamp = {Wed, 24 Nov 2021 09:22:55 +0100},
biburl = {https://dblp.org/rec/conf/icce-tw/Chen20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/ChangHWC20,
author = {Hao{-}Chun Chang and
Li{-}An Huang and
Kai{-}Chiang Wu and
Yu{-}Guang Chen},
editor = {William Swartz and
Jens Lienig},
title = {Selective Sensor Placement for Cost-Effective Online Aging Monitoring
and Resilience},
booktitle = {{ISPD} 2020: International Symposium on Physical Design, Taipei, Taiwan,
March 29 - April 1, 2020, delayed to September 20-23, 2020},
pages = {95--102},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3372780.3375556},
doi = {10.1145/3372780.3375556},
timestamp = {Sun, 22 Mar 2020 19:04:23 +0100},
biburl = {https://dblp.org/rec/conf/ispd/ChangHWC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ChenLL20,
author = {Yu{-}Guang Chen and
Yu{-}Yi Lin and
Ing{-}Chao Lin},
title = {An NBTI-aware Task Parallelism Scheme for Improving Lifespan of Multi-core
Systems},
booktitle = {21st International Symposium on Quality Electronic Design, {ISQED}
2020, Santa Clara, CA, USA, March 25-26, 2020},
pages = {117--122},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISQED48828.2020.9137005},
doi = {10.1109/ISQED48828.2020.9137005},
timestamp = {Wed, 22 Jul 2020 15:06:46 +0200},
biburl = {https://dblp.org/rec/conf/isqed/ChenLL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChenLK19,
author = {Yu{-}Guang Chen and
Ing{-}Chao Lin and
Jian{-}Ting Ke},
editor = {David Z. Pan},
title = {{ROAD:} Improving Reliability of Multi-core System via Asymmetric
Aging},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2019, Westminster, CO, USA, November 4-7, 2019},
pages = {1--8},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1109/ICCAD45719.2019.8942178},
doi = {10.1109/ICCAD45719.2019.8942178},
timestamp = {Wed, 19 Feb 2020 16:38:01 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ChenLK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/HuangCW19,
author = {Ning{-}Chi Huang and
Yu{-}Guang Chen and
Kai{-}Chiang Wu},
title = {Exploration and Exploitation of Dual Timing Margins for Improving
Power Efficiency of Variable-Latency Designs},
booktitle = {2019 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2019,
Miami, FL, USA, July 15-17, 2019},
pages = {218--223},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISVLSI.2019.00048},
doi = {10.1109/ISVLSI.2019.00048},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/HuangCW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChiuCL18,
author = {Kun{-}Wei Chiu and
Yu{-}Guang Chen and
Ing{-}Chao Lin},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {An efficient NBTI-aware wake-up strategy for power-gated designs},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {901--904},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342136},
doi = {10.23919/DATE.2018.8342136},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/ChiuCL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChenSSSC17,
author = {Yu{-}Guang Chen and
Michihiro Shintani and
Takashi Sato and
Yiyu Shi and
Shih{-}Chieh Chang},
title = {Pattern based runtime voltage emergency prediction: An instruction-aware
block sparse compressed sensing approach},
booktitle = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2017, Chiba, Japan, January 16-19, 2017},
pages = {543--548},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASPDAC.2017.7858380},
doi = {10.1109/ASPDAC.2017.7858380},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ChenSSSC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChenWWLC16,
author = {Yu{-}Guang Chen and
Wan{-}Yu Wen and
Yun{-}Ting Wang and
You{-}Luen Lee and
Shih{-}Chieh Chang},
title = {A novel low-cost dynamic logic reconfigurable structure strategy for
low power optimization},
booktitle = {21st Asia and South Pacific Design Automation Conference, {ASP-DAC}
2016, Macao, Macao, January 25-28, 2016},
pages = {250--255},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASPDAC.2016.7428019},
doi = {10.1109/ASPDAC.2016.7428019},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ChenWWLC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenWSHC15,
author = {Yu{-}Guang Chen and
Wan{-}Yu Wen and
Yiyu Shi and
Wing{-}Kai Hon and
Shih{-}Chieh Chang},
title = {Novel Spare {TSV} Deployment for 3-D ICs Considering Yield and Timing
Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {34},
number = {4},
pages = {577--588},
year = {2015},
url = {https://doi.org/10.1109/TCAD.2014.2385759},
doi = {10.1109/TCAD.2014.2385759},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChenWSHC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/ChenWWSC15,
author = {Yu{-}Guang Chen and
Wan{-}Yu Wen and
Tao Wang and
Yiyu Shi and
Shih{-}Chieh Chang},
editor = {Azadeh Davoodi and
Evangeline F. Y. Young},
title = {Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful
Degradation},
booktitle = {Proceedings of the 2015 Symposium on International Symposium on Physical
Design, {ISPD} 2015, Monterey, CA, USA, March 29 - April 1, 2015},
pages = {41--48},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2717764.2717765},
doi = {10.1145/2717764.2717765},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/ChenWWSC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenGLSC14,
author = {Yu{-}Guang Chen and
Hui Geng and
Kuan{-}Yu Lai and
Yiyu Shi and
Shih{-}Chieh Chang},
title = {Multibit Retention Registers for Power Gated Designs: Concept, Design,
and Deployment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {507--518},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2293881},
doi = {10.1109/TCAD.2013.2293881},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChenGLSC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChenWLWSC14,
author = {Yu{-}Guang Chen and
Tao Wang and
Kuan{-}Yu Lai and
Wan{-}Yu Wen and
Yiyu Shi and
Shih{-}Chieh Chang},
title = {Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful
Degradation in Sub-Threshold Designs},
booktitle = {The 51st Annual Design Automation Conference 2014, {DAC} '14, San
Francisco, CA, USA, June 1-5, 2014},
pages = {98:1--98:6},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2593069.2593115},
doi = {10.1145/2593069.2593115},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ChenWLWSC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChenLLSHC14,
author = {Yu{-}Guang Chen and
Kuan{-}Yu Lai and
Ming{-}Chao Lee and
Yiyu Shi and
Wing{-}Kai Hon and
Shih{-}Chieh Chang},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Yield and timing constrained spare {TSV} assignment for three-dimensional
integrated circuits},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--4},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.118},
doi = {10.7873/DATE.2014.118},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/ChenLLSHC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChenSLHC12,
author = {Yu{-}Guang Chen and
Yiyu Shi and
Kuan{-}Yu Lai and
Hui Geng and
Shih{-}Chieh Chang},
editor = {Alan J. Hu},
title = {Efficient multiple-bit retention register assignment for power gated
design: Concept and algorithms},
booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012},
pages = {309--316},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2429384.2429448},
doi = {10.1145/2429384.2429448},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ChenSLHC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/LeeSCMC12,
author = {Ming{-}Chao Lee and
Yiyu Shi and
Yu{-}Guang Chen and
Diana Marculescu and
Shih{-}Chieh Chang},
editor = {Jiang Hu and
Cheng{-}Kok Koh},
title = {Efficient on-line module-level wake-up scheduling for high performance
multi-module designs},
booktitle = {International Symposium on Physical Design, ISPD'12, Napa, CA, USA,
March 25-28, 2012},
pages = {97--104},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2160916.2160939},
doi = {10.1145/2160916.2160939},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/LeeSCMC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LeeCHC11,
author = {Ming{-}Chao Lee and
Yu{-}Guang Chen and
Ding{-}Kei Huang and
Shih{-}Chieh Chang},
title = {NBTI-aware power gating design},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {609--614},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722261},
doi = {10.1109/ASPDAC.2011.5722261},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LeeCHC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijautcomp/LiuWCL10,
author = {Shuxi Liu and
Ming{-}Yu Wang and
Yu{-}Guang Chen and
Shan Li},
title = {A novel fuzzy direct torque control system for three-level inverter-fed
induction machine},
journal = {Int. J. Autom. Comput.},
volume = {7},
number = {1},
pages = {78--85},
year = {2010},
url = {https://doi.org/10.1007/s11633-010-0078-7},
doi = {10.1007/S11633-010-0078-7},
timestamp = {Tue, 18 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijautcomp/LiuWCL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwcmc/WangYLYOHC06,
author = {Chun{-}Hsin Wang and
Chang{-}Wu Yu and
Chiu{-}Kuo Liang and
Kun{-}Ming Yu and
Wen Ouyang and
Ching{-}Hsien Hsu and
Yu{-}Guang Chen},
editor = {Seizo Onoe and
Mohsen Guizani and
Hsiao{-}Hwa Chen and
Mamoru Sawahashi},
title = {Tracers placement for {IP} traceback against DDoS attacks},
booktitle = {Proceedings of the International Conference on Wireless Communications
and Mobile Computing, {IWCMC} 2006, Vancouver, British Columbia, Canada,
July 3-6, 2006},
pages = {355--360},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1143549.1143620},
doi = {10.1145/1143549.1143620},
timestamp = {Fri, 22 Nov 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iwcmc/WangYLYOHC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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