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ORCIDBibTeX records: Meng-Fan Chang
@article{DBLP:journals/jssc/LeleCSCKWBKCCR24,
author = {Ashwin Sanjay Lele and
Muya Chang and
Samuel D. Spetalnick and
Brian Crafton and
Shota Konno and
Zishen Wan and
Ashwin Bhat and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {A Heterogeneous {RRAM} In-Memory and {SRAM} Near-Memory SoC for Fused
Frame and Event-Based Target Identification and Tracking},
journal = {{IEEE} J. Solid State Circuits},
volume = {59},
number = {1},
pages = {52--64},
year = {2024},
url = {https://doi.org/10.1109/JSSC.2023.3297411},
doi = {10.1109/JSSC.2023.3297411},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/LeleCSCKWBKCCR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HsuWHKLJCCLLTHCCC24,
author = {Hung{-}Hsi Hsu and
Tai{-}Hao Wen and
Wei{-}Hsing Huang and
Win{-}San Khwa and
Yun{-}Chen Lo and
Chuan{-}Jia Jhang and
Yu{-}Hsiang Chin and
Yu{-}Chiao Chen and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Kea{-}Tiong Tang and
Chih{-}Cheng Hsieh and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {A Nonvolatile AI-Edge Processor With {SLC-MLC} Hybrid ReRAM Compute-in-Memory
Macro Using Current-Voltage-Hybrid Readout Scheme},
journal = {{IEEE} J. Solid State Circuits},
volume = {59},
number = {1},
pages = {116--127},
year = {2024},
url = {https://doi.org/10.1109/JSSC.2023.3314433},
doi = {10.1109/JSSC.2023.3314433},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/HsuWHKLJCCLLTHCCC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WuSHRCCKHLSLCLLHTC24,
author = {Ping{-}Chun Wu and
Jian{-}Wei Su and
Li{-}Yang Hong and
Jin{-}Sheng Ren and
Chih{-}Han Chien and
Ho{-}Yu Chen and
Chao{-}En Ke and
Hsu{-}Ming Hsiao and
Sih{-}Han Li and
Shyh{-}Shyuan Sheu and
Wei{-}Chung Lo and
Shih{-}Chieh Chang and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Meng{-}Fan Chang},
title = {A Floating-Point 6T {SRAM} In-Memory-Compute Macro Using Hybrid-Domain
Structure for Advanced {AI} Edge Chips},
journal = {{IEEE} J. Solid State Circuits},
volume = {59},
number = {1},
pages = {196--207},
year = {2024},
url = {https://doi.org/10.1109/JSSC.2023.3309966},
doi = {10.1109/JSSC.2023.3309966},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/WuSHRCCKHLSLCLLHTC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/YouCKLHCLLHTCCC24,
author = {De{-}Qi You and
Yen{-}Cheng Chiu and
Win{-}San Khwa and
Chung{-}Yuan Li and
Fang{-}Ling Hsieh and
Yu{-}An Chien and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {An 8b-Precision 8-Mb {STT-MRAM} Near-Memory-Compute Macro Using Weight-Feature
and Input-Sparsity Aware Schemes for Energy-Efficient Edge {AI} Devices},
journal = {{IEEE} J. Solid State Circuits},
volume = {59},
number = {1},
pages = {219--230},
year = {2024},
url = {https://doi.org/10.1109/JSSC.2023.3324335},
doi = {10.1109/JSSC.2023.3324335},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/YouCKLHCLLHTCCC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/YueLFHWYZLSCWHCSDLLY24,
author = {Jinshan Yue and
Yongpan Liu and
Xiaoyu Feng and
Yifan He and
Jingyu Wang and
Zhe Yuan and
Mingtao Zhan and
Jiaxin Liu and
Jian{-}Wei Su and
Yen{-}Lin Chung and
Ping{-}Chun Wu and
Li{-}Yang Hong and
Meng{-}Fan Chang and
Nan Sun and
Chunmeng Dou and
Xueqing Li and
Ming Liu and
Huazhong Yang},
title = {An Energy-Efficient Computing-in-Memory {NN} Processor With Set-Associate
Blockwise Sparsity and Ping-Pong Weight Update},
journal = {{IEEE} J. Solid State Circuits},
volume = {59},
number = {5},
pages = {1612--1627},
year = {2024},
url = {https://doi.org/10.1109/JSSC.2023.3324954},
doi = {10.1109/JSSC.2023.3324954},
timestamp = {Mon, 06 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/YueLFHWYZLSCWHCSDLLY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SunCCAMFNCCWC24,
author = {Xiaoyu Sun and
Weidong Cao and
Brian Crafton and
Kerem Akarvardar and
Haruki Mori and
Hidehiro Fujiwara and
Hiroki Noguchi and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Yih Wang and
Tsung{-}Yung Jonathan Chang},
title = {Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory
Macros},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {43},
number = {4},
pages = {1191--1205},
year = {2024},
url = {https://doi.org/10.1109/TCAD.2023.3333290},
doi = {10.1109/TCAD.2023.3333290},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SunCCAMFNCCWC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasII/SuLWCLCHRHCMLSLCHLLHTC24,
author = {Jian{-}Wei Su and
Pei{-}Jung Lu and
Ping{-}Chun Wu and
Yen{-}Chi Chou and
Ta{-}Wei Liu and
Yen{-}Lin Chung and
Li{-}Yang Hung and
Jin{-}Sheng Ren and
Wei{-}Hsing Huang and
Chih{-}Han Chien and
Peng{-}I Mei and
Sih{-}Han Li and
Shyh{-}Shyuan Sheu and
Wei{-}Chung Lo and
Shih{-}Chieh Chang and
Hao{-}Chiao Hong and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Meng{-}Fan Chang},
title = {8-Bit Precision 6T {SRAM} Compute-in-Memory Macro Using Global Bitline-Combining
Scheme for Edge {AI} Chips},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {71},
number = {4},
pages = {2304--2308},
year = {2024},
url = {https://doi.org/10.1109/TCSII.2023.3331375},
doi = {10.1109/TCSII.2023.3331375},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasII/SuLWCLCHRHCMLSLCHLLHTC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SpetalnickLCCRYHAKCCR24,
author = {Samuel D. Spetalnick and
Ashwin Sanjay Lele and
Brian Crafton and
Muya Chang and
Sigang Ryu and
Jong{-}Hyeok Yoon and
Zhijian Hao and
Azadeh Ansari and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {30.1 {A} 40nm {VLIW} Edge Accelerator with 5MB of 0.256pJ/b {RRAM}
and a Localization Solver for Bristle Robot Surveillance},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {482--484},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454500},
doi = {10.1109/ISSCC49657.2024.10454500},
timestamp = {Tue, 19 Mar 2024 09:04:31 +0100},
biburl = {https://dblp.org/rec/conf/isscc/SpetalnickLCCRYHAKCCR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KhwaWWSCKCHCCLLHTC24,
author = {Win{-}San Khwa and
Ping{-}Chun Wu and
Jui{-}Jen Wu and
Jian{-}Wei Su and
Ho{-}Yu Chen and
Zhao{-}En Ke and
Ting{-}Chien Chiu and
Jun{-}Ming Hsu and
Chiao{-}Yen Cheng and
Yu{-}Chen Chen and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Meng{-}Fan Chang},
title = {34.2 {A} 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory
Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge
Devices},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {568--570},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454447},
doi = {10.1109/ISSCC49657.2024.10454447},
timestamp = {Tue, 19 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KhwaWWSCKCHCCLLHTC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WenHKHKCWCHLLHTTCCCC24,
author = {Tai{-}Hao Wen and
Hung{-}Hsi Hsu and
Win{-}San Khwa and
Wei{-}Hsing Huang and
Zhao{-}En Ke and
Yu{-}Hsiang Chin and
Hua{-}Jin Wen and
Yu{-}Chen Chang and
Wei{-}Ting Hsu and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Shih{-}Hsih Teng and
Chung{-}Cheng Chou and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {34.8 {A} 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with
31.2TFLOPS/W for {AI} Edge Devices},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {580--582},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454468},
doi = {10.1109/ISSCC49657.2024.10454468},
timestamp = {Tue, 19 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/WenHKHKCWCHLLHTTCCCC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HungWHHCSKLLHTC23,
author = {Je{-}Min Hung and
Tai{-}Hao Wen and
Yen{-}Hsiang Huang and
Sheng{-}Po Huang and
Fu{-}Chun Chang and
Chin{-}I Su and
Win{-}San Khwa and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free
Time-Domain Readout Scheme for {AI} Edge Devices},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {1},
pages = {303--315},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2022.3200515},
doi = {10.1109/JSSC.2022.3200515},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/HungWHHCSKLLHTC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/GuoYSLHTWSLCLWY23,
author = {Ruiqi Guo and
Zhiheng Yue and
Xin Si and
Hao Li and
Te Hu and
Limei Tang and
Yabing Wang and
Hao Sun and
Leibo Liu and
Meng{-}Fan Chang and
Qiang Li and
Shaojun Wei and
Shouyi Yin},
title = {TT@CIM: {A} Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity
Optimization and Variable Precision Quantization},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {3},
pages = {852--866},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2022.3198413},
doi = {10.1109/JSSC.2022.3198413},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/GuoYSLHTWSLCLWY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SuCLLLWCHRPJHCMLSCLWSLLHTC23,
author = {Jian{-}Wei Su and
Yen{-}Chi Chou and
Ruhui Liu and
Ta{-}Wei Liu and
Pei{-}Jung Lu and
Ping{-}Chun Wu and
Yen{-}Lin Chung and
Li{-}Yang Hong and
Jin{-}Sheng Ren and
Tianlong Pan and
Chuan{-}Jia Jhang and
Wei{-}Hsing Huang and
Chih{-}Han Chien and
Peng{-}I Mei and
Sih{-}Han Li and
Shyh{-}Shyuan Sheu and
Shih{-}Chieh Chang and
Wei{-}Chung Lo and
Chih{-}I Wu and
Xin Si and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Meng{-}Fan Chang},
title = {A 8-b-Precision 6T {SRAM} Computing-in-Memory Macro Using Segmented-Bitline
Charge-Sharing Scheme for {AI} Edge Chips},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {3},
pages = {877--892},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2022.3199077},
doi = {10.1109/JSSC.2022.3199077},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SuCLLLWCHRPJHCMLSCLWSLLHTC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChiuCHLLTCH23,
author = {Min{-}Yang Chiu and
Guan{-}Cheng Chen and
Tzu{-}Hsiang Hsu and
Ren{-}Shuo Liu and
Chung{-}Chuan Lo and
Kea{-}Tiong Tang and
Meng{-}Fan Chang and
Chih{-}Cheng Hsieh},
title = {A Multimode Vision Sensor With Temporal Contrast Pixel and Column-Parallel
Local Binary Pattern Extraction for Dynamic Depth Sensing Using Stereo
Vision},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {10},
pages = {2767--2777},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2023.3292051},
doi = {10.1109/JSSC.2023.3292051},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChiuCHLLTCH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HsuCCLLTCH23,
author = {Tzu{-}Hsiang Hsu and
Guan{-}Cheng Chen and
Yi{-}Ren Chen and
Ren{-}Shuo Liu and
Chung{-}Chuan Lo and
Kea{-}Tiong Tang and
Meng{-}Fan Chang and
Chih{-}Cheng Hsieh},
title = {A 0.8 {V} Intelligent Vision Sensor With Tiny Convolutional Neural
Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor
Technique for Image Classification},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {11},
pages = {3266--3274},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2023.3285734},
doi = {10.1109/JSSC.2023.3285734},
timestamp = {Thu, 09 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/HsuCCLLTCH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/UptonLSRKCCMRM23,
author = {Luke R. Upton and
Akash Levy and
Michael D. Scott and
Dennis Rich and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Subhasish Mitra and
Priyanka Raina and
Boris Murmann},
title = {{EMBER:} {A} 100 MHz, 0.86 mm\({}^{\mbox{2}}\), Multiple-Bits-per-Cell
{RRAM} Macro in 40 nm {CMOS} with Compact Peripherals and 1.0 pJ/bit
Read Circuitry},
booktitle = {49th {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2023,
Lisbon, Portugal, September 11-14, 2023},
pages = {469--472},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ESSCIRC59616.2023.10268807},
doi = {10.1109/ESSCIRC59616.2023.10268807},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/UptonLSRKCCMRM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/JiWWKCHC23,
author = {Zexi Ji and
Hanrui Wang and
Miaorong Wang and
Win{-}San Khwa and
Meng{-}Fan Chang and
Song Han and
Anantha P. Chandrakasan},
title = {A Fully-Integrated Energy-Scalable Transformer Accelerator Supporting
Adaptive Model Configuration and Word Elimination for Language Understanding
on Edge Devices},
booktitle = {{IEEE/ACM} International Symposium on Low Power Electronics and Design,
{ISLPED} 2023, Vienna, Austria, August 7-8, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISLPED58423.2023.10244459},
doi = {10.1109/ISLPED58423.2023.10244459},
timestamp = {Fri, 09 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/JiWWKCHC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WuSHRCCKHLSLCLLHTC23,
author = {Ping{-}Chun Wu and
Jian{-}Wei Su and
Li{-}Yang Hong and
Jin{-}Sheng Ren and
Chih{-}Han Chien and
Ho{-}Yu Chen and
Chao{-}En Ke and
Hsu{-}Ming Hsiao and
Sih{-}Han Li and
Shyh{-}Shyuan Sheu and
Wei{-}Chung Lo and
Shih{-}Chieh Chang and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Meng{-}Fan Chang},
title = {A 22nm 832Kb Hybrid-Domain Floating-Point {SRAM} In-Memory-Compute
Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {126--127},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067527},
doi = {10.1109/ISSCC42615.2023.10067527},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/WuSHRCCKHLSLCLLHTC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HuangWHKLJHCCLLTHCCC23,
author = {Wei{-}Hsing Huang and
Tai{-}Hao Wen and
Je{-}Min Hung and
Win{-}San Khwa and
Yun{-}Chen Lo and
Chuan{-}Jia Jhang and
Hung{-}Hsi Hsu and
Yu{-}Hsiang Chin and
Yu{-}Chiao Chen and
Chuna{-}Chuan Lo and
Ren{-}Shuo Liu and
Kea{-}Tiong Tang and
Chih{-}Cheng Hsieh and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {A Nonvolatile Al-Edge Processor with 4MB {SLC-MLC} Hybrid-Mode ReRAM
Compute-in-Memory Macro and 51.4-251TOPS/W},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {258--259},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067610},
doi = {10.1109/ISSCC42615.2023.10067610},
timestamp = {Mon, 08 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/HuangWHKLJHCCLLTHCCC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangLSCKWBKCCR23,
author = {Muya Chang and
Ashwin Sanjay Lele and
Samuel D. Spetalnick and
Brian Crafton and
Shota Konno and
Zishen Wan and
Ashwin Bhat and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {A 73.53TOPS/W 14.74TOPS Heterogeneous {RRAM} In-Memory and {SRAM}
Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {426--427},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067544},
doi = {10.1109/ISSCC42615.2023.10067544},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChangLSCKWBKCCR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChiuKLHCLCPYCLLLHTCCC23,
author = {Yen{-}Cheng Chiu and
Win{-}San Khwa and
Chung{-}Yuan Li and
Fang{-}Ling Hsieh and
Yu{-}An Chien and
Guan{-}Yi Lin and
Po{-}Jung Chen and
Tsen{-}Hsiang Pan and
De{-}Qi You and
Fang{-}Yi Chen and
Andrew Lee and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {A 22nm 8Mb {STT-MRAM} Near-Memory-Computing Macro with 8b-Precision
and 46.4-160.1TOPS/W for Edge-AI Devices},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {496--497},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067563},
doi = {10.1109/ISSCC42615.2023.10067563},
timestamp = {Wed, 29 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChiuKLHCLCPYCLLLHTCCC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/HsuWWJYCC23,
author = {Hung{-}Hsi Hsu and
Tai{-}Hao Wen and
Ping{-}Chun Wu and
Chuan{-}Jia Jhang and
De{-}Qi You and
Ping{-}Cheng Chen and
Meng{-}Fan Chang},
title = {Challenges in Circuits of Nonvolatile Compute-In-Memory for Edge {AI}
Chips},
booktitle = {66th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2023, Tempe, AZ, USA, August 6-9, 2023},
pages = {98--102},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/MWSCAS57524.2023.10405877},
doi = {10.1109/MWSCAS57524.2023.10405877},
timestamp = {Sat, 24 Feb 2024 20:42:53 +0100},
biburl = {https://dblp.org/rec/conf/mwscas/HsuWWJYCC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/SpetalnickCKCLK23,
author = {Samuel D. Spetalnick and
Muya Chang and
Shota Konno and
Brian Crafton and
Ashwin Sanjay Lele and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {A 2.38 MCells/mm\({}^{\mbox{2}}\) 9.81 -350 {TOPS/W} {RRAM} Compute-in-Memory
Macro in 40nm {CMOS} with Hybrid Offset/IOFF Cancellation and {ICELL}
{RBLSL} Drop Mitigation},
booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits), Kyoto, Japan, June 11-16, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185424},
doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185424},
timestamp = {Fri, 28 Jul 2023 10:40:41 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/SpetalnickCKCLK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/WenHHWCLCSKWLLH23,
author = {Tai{-}Hao Wen and
Je{-}Min Hung and
Hung{-}Hsi Hsu and
Yuan Wu and
Fu{-}Chun Chang and
Chung{-}Yuan Li and
Chih{-}Han Chien and
Chin{-}I Su and
Win{-}San Khwa and
Jui{-}Jen Wu and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Mon{-}Shu Ho and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {A 28nm Nonvolatile {AI} Edge Processor using 4Mb Analog-Based Near-Memory-Compute
ReRAM with 27.2 {TOPS/W} for Tiny {AI} Edge Devices},
booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits), Kyoto, Japan, June 11-16, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185326},
doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185326},
timestamp = {Tue, 20 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsit/WenHHWCLCSKWLLH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/nanoarch/2023,
editor = {Ronald Tetzlaff and
Fernando Corinto and
Neil Kemp and
Alon Ascoli and
Andreas M{\"{o}}gel and
Meng{-}Fan Marvin Chang and
Joseph S. Friedman and
Siting Liu and
John Paul Strachan and
Stephan Menzel and
Mehdi B. Tahoori and
Martin Ziegler and
Jason Eshraghian and
Ioannis Messaris and
Christian Koitzsch and
Thomas Mikolajick and
Vasileios G. Ntinas},
title = {Proceedings of the 18th {ACM} International Symposium on Nanoscale
Architectures, {NANOARCH} 2023, Dresden, Germany, December 18-20,
2023},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3611315},
doi = {10.1145/3611315},
timestamp = {Fri, 26 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nanoarch/2023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/YoonCKCCR22,
author = {Jong{-}Hyeok Yoon and
Muya Chang and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {A 40-nm, 64-Kb, 56.67 {TOPS/W} Voltage-Sensing Computing-In-Memory/Digital
{RRAM} Macro Supporting Iterative Write With Verification and Online
Read-Disturb Detection},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {1},
pages = {68--79},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2021.3101209},
doi = {10.1109/JSSC.2021.3101209},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/YoonCKCCR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SuSCCHTLLLWCRCW22,
author = {Jian{-}Wei Su and
Xin Si and
Yen{-}Chi Chou and
Ting{-}Wei Chang and
Wei{-}Hsing Huang and
Yung{-}Ning Tu and
Ruhui Liu and
Pei{-}Jung Lu and
Ta{-}Wei Liu and
Jing{-}Hong Wang and
Yen{-}Lin Chung and
Jin{-}Sheng Ren and
Fu{-}Chun Chang and
Yuan Wu and
Hongwu Jiang and
Shanshi Huang and
Sih{-}Han Li and
Shyh{-}Shyuan Sheu and
Chih{-}I Wu and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Shimeng Yu and
Meng{-}Fan Chang},
title = {Two-Way Transpose Multibit 6T {SRAM} Computing-in-Memory Macro for
Inference-Training {AI} Edge Chips},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {2},
pages = {609--624},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2021.3108344},
doi = {10.1109/JSSC.2021.3108344},
timestamp = {Tue, 20 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/SuSCCHTLLLWCRCW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/YoonCKCCR22a,
author = {Jong{-}Hyeok Yoon and
Muya Chang and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory {RRAM} Macro
With Write Verification and Multi-Bit Encoding},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {3},
pages = {845--857},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2022.3141370},
doi = {10.1109/JSSC.2022.3141370},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/YoonCKCCR22a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/PrabhuGKRGKDKLL22,
author = {Kartik Prabhu and
Albert Gural and
Zainab F. Khan and
Robert M. Radway and
Massimo Giordano and
Kalhan Koul and
Rohan Doshi and
John W. Kustin and
Timothy Liu and
Gregorio B. Lopes and
Victor Turbiner and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Gu{\'{e}}nol{\'{e}} Lallement and
Boris Murmann and
Subhasish Mitra and
Priyanka Raina},
title = {{CHIMERA:} {A} 0.92-TOPS, 2.2-TOPS/W Edge {AI} Accelerator With 2-MByte
On-Chip Foundry Resistive {RAM} for Efficient Training and Inference},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {4},
pages = {1013--1026},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2022.3140753},
doi = {10.1109/JSSC.2022.3140753},
timestamp = {Wed, 18 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/PrabhuGKRGKDKLL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChiuCLHCXWKCHTL22,
author = {Yen{-}Cheng Chiu and
Tung{-}Cheng Chang and
Chun{-}Ying Lee and
Je{-}Min Hung and
Kuang{-}Tang Chang and
Cheng{-}Xin Xue and
Ssu{-}Yen Wu and
Hui{-}Yao Kao and
Peng Chen and
Hsiao{-}Yu Huang and
Shih{-}Hsih Teng and
Chieh{-}Pu Lo and
Yi{-}Chun Shih and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Yier Jin and
Meng{-}Fan Chang},
title = {A 22-nm 1-Mb 1024-b Read Data-Protected {STT-MRAM} Macro With Near-Memory
Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware
Mobile Device},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {6},
pages = {1936--1949},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2021.3112182},
doi = {10.1109/JSSC.2021.3112182},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChiuCLHCXWKCHTL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/YueLYFHSZSLWCDL22,
author = {Jinshan Yue and
Yongpan Liu and
Zhe Yuan and
Xiaoyu Feng and
Yifan He and
Wenyu Sun and
Zhixiao Zhang and
Xin Si and
Ruhui Liu and
Zi Wang and
Meng{-}Fan Chang and
Chunmeng Dou and
Xueqing Li and
Ming Liu and
Huazhong Yang},
title = {{STICKER-IM:} {A} 65 nm Computing-in-Memory {NN} Processor Using Block-Wise
Sparsity Optimization and Inter/Intra-Macro Data Reuse},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {8},
pages = {2560--2573},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2022.3148273},
doi = {10.1109/JSSC.2022.3148273},
timestamp = {Mon, 08 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/YueLYFHSZSLWCDL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SieLCYLLHCT22,
author = {Syuan{-}Hao Sie and
Jye{-}Luen Lee and
Yi{-}Ren Chen and
Zuo{-}Wei Yeh and
Zhaofang Li and
Chih{-}Cheng Lu and
Chih{-}Cheng Hsieh and
Meng{-}Fan Chang and
Kea{-}Tiong Tang},
title = {{MARS:} Multimacro Architecture {SRAM} CIM-Based Accelerator With
Co-Designed Compressed Neural Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {5},
pages = {1550--1562},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3082107},
doi = {10.1109/TCAD.2021.3082107},
timestamp = {Tue, 26 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SieLCYLLHCT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/LinCYLLHCLCTN22,
author = {Wei{-}Ting Lin and
Hsiang{-}Yun Cheng and
Chia{-}Lin Yang and
Meng{-}Yao Lin and
Kai Lien and
Han{-}Wen Hu and
Hung{-}Sheng Chang and
Hsiang{-}Pang Li and
Meng{-}Fan Chang and
Yen{-}Ting Tsou and
Chin{-}Fu Nien},
title = {{DL-RSIM:} {A} Reliability and Deployment Strategy Simulation Framework
for ReRAM-based {CNN} Accelerators},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {21},
number = {3},
pages = {24:1--24:29},
year = {2022},
url = {https://doi.org/10.1145/3507639},
doi = {10.1145/3507639},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/LinCYLLHCLCTN22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aicas/HsiehLLLCT22,
author = {Chia{-}Yu Hsieh and
Shih{-}Ting Lin and
Zhaofang Li and
Chih{-}Cheng Lu and
Meng{-}Fan Chang and
Kea{-}Tiong Tang},
title = {MARSv2: Multicore and Programmable Reconstruction Architecture {SRAM}
CIM-Based Accelerator with Lightweight Network},
booktitle = {4th {IEEE} International Conference on Artificial Intelligence Circuits
and Systems, {AICAS} 2022, Incheon, Republic of Korea, June 13-15,
2022},
pages = {383--386},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/AICAS54282.2022.9870005},
doi = {10.1109/AICAS54282.2022.9870005},
timestamp = {Fri, 16 Sep 2022 20:28:36 +0200},
biburl = {https://dblp.org/rec/conf/aicas/HsiehLLLCT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/KuoWLLCT22,
author = {Hao{-}Wen Kuo and
Rui{-}Hsuan Wang and
Zhaofang Li and
Shih{-}Ting Lin and
Meng{-}Fan Chang and
Kea{-}Tiong Tang},
title = {A Two-stage Training Framework for Hardware Constraints of Computing-in-Memory
Architecture},
booktitle = {{IEEE} Asia Pacific Conference on Circuit and Systems, {APCCAS} 2022,
Shenzhen, China, November 11-13, 2022},
pages = {30--34},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/APCCAS55924.2022.10090308},
doi = {10.1109/APCCAS55924.2022.10090308},
timestamp = {Sat, 22 Apr 2023 16:25:51 +0200},
biburl = {https://dblp.org/rec/conf/apccas/KuoWLLCT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/LiWSZYWHNZLZCGS22,
author = {Xingchen Li and
Bingzhe Wu and
Guangyu Sun and
Zhe Zhang and
Zhihang Yuan and
Runsheng Wang and
Ru Huang and
Dimin Niu and
Hongzhong Zheng and
Zhichao Lu and
Liang Zhao and
Meng{-}Fan Marvin Chang and
Tianchan Guan and
Xin Si},
title = {Enabling High-Quality Uncertainty Quantification in a {PIM} Designed
for Bayesian Neural Network},
booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture,
{HPCA} 2022, Seoul, South Korea, April 2-6, 2022},
pages = {1043--1055},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/HPCA53966.2022.00080},
doi = {10.1109/HPCA53966.2022.00080},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hpca/LiWSZYWHNZLZCGS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChangHCW22,
author = {Meng{-}Fan Chang and
Je{-}Ming Hung and
Ping{-}Cheng Chen and
Tai{-}Hao Wen},
editor = {Tulika Mitra and
Evangeline F. Y. Young and
Jinjun Xiong},
title = {Reliable Computing of ReRAM Based Compute-in-Memory Circuits for {AI}
Edge Devices},
booktitle = {Proceedings of the 41st {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2022, San Diego, California, USA, 30 October 2022
- 3 November 2022},
pages = {158:1--158:6},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3508352.3561119},
doi = {10.1145/3508352.3561119},
timestamp = {Tue, 06 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/ChangHCW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangSCKCCR22,
author = {Muya Chang and
Samuel D. Spetalnick and
Brian Crafton and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB
{RRAM/SRAM} System with Embedded Cortex {M3} Microprocessor for Edge
Recommendation Systems},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731679},
doi = {10.1109/ISSCC42614.2022.9731679},
timestamp = {Mon, 21 Mar 2022 13:32:47 +0100},
biburl = {https://dblp.org/rec/conf/isscc/ChangSCKCCR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HsuCCLLCTH22,
author = {Tzu{-}Hsiang Hsu and
Guan{-}Cheng Chen and
Yi{-}Ren Chen and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Meng{-}Fan Chang and
Kea{-}Tiong Tang and
Chih{-}Cheng Hsieh},
title = {A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network
and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique
for Image Classification},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731675},
doi = {10.1109/ISSCC42614.2022.9731675},
timestamp = {Mon, 21 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/HsuCCLLCTH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HungHHCWSKLLHTC22,
author = {Je{-}Min Hung and
Yen{-}Hsiang Huang and
Sheng{-}Po Huang and
Fu{-}Chun Chang and
Tai{-}Hao Wen and
Chin{-}I Su and
Win{-}San Khwa and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory
Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI
Devices},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731715},
doi = {10.1109/ISSCC42614.2022.9731715},
timestamp = {Mon, 21 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/HungHHCWSKLLHTC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KhwaCJHLWCYLC22,
author = {Win{-}San Khwa and
Yen{-}Cheng Chiu and
Chuan{-}Jia Jhang and
Sheng{-}Po Huang and
Chun{-}Ying Lee and
Tai{-}Hao Wen and
Fu{-}Chun Chang and
Shao{-}Ming Yu and
Tung{-}Yin Lee and
Meng{-}Fan Chang},
title = {A 40-nm, 2M-Cell, 8b-Precision, Hybrid {SLC-MLC} {PCM} Computing-in-Memory
Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731670},
doi = {10.1109/ISSCC42614.2022.9731670},
timestamp = {Mon, 21 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KhwaCJHLWCYLC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SpetalnickCCKCC22,
author = {Samuel D. Spetalnick and
Muya Chang and
Brian Crafton and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {A 40nm 64kb 26.56TOPS/W 2.37Mb/mm\({}^{\mbox{2}}\)RRAM Binary/Compute-in-Memory
Macro with 4.23x Improvement in Density and {\textgreater}75{\%} Use
of Sensing Dynamic Range},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731725},
doi = {10.1109/ISSCC42614.2022.9731725},
timestamp = {Mon, 21 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/SpetalnickCCKCC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WuSCHRCWCLHLSCL22,
author = {Ping{-}Chun Wu and
Jian{-}Wei Su and
Yen{-}Lin Chung and
Li{-}Yang Hong and
Jin{-}Sheng Ren and
Fu{-}Chun Chang and
Yuan Wu and
Ho{-}Yu Chen and
Chen{-}Hsun Lin and
Hsu{-}Ming Hsiao and
Sih{-}Han Li and
Shyh{-}Shyuan Sheu and
Shih{-}Chieh Chang and
Wei{-}Chung Lo and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Chih{-}I Wu and
Meng{-}Fan Chang},
title = {A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns
Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI
Devices},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731681},
doi = {10.1109/ISSCC42614.2022.9731681},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/WuSCHRCWCLHLSCL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HuWCLLWLLHHLC0L22,
author = {Han{-}Wen Hu and
Wei{-}Chen Wang and
Chung Kuang Chen and
Yung{-}Chun Lee and
Bo{-}Rong Lin and
Huai{-}Mu Wang and
Yen{-}Po Lin and
Yu{-}Chao Lin and
Chih{-}Chang Hsieh and
Chia{-}Ming Hu and
Yi{-}Ting Lai and
Han{-}Sung Chen and
Yuan{-}Hao Chang and
Hsiang{-}Pang Li and
Tei{-}Wei Kuo and
Keh{-}Chung Wang and
Meng{-}Fan Chang and
Chun{-}Hsiung Hung and
Chih{-}Yuan Lu},
title = {A 512Gb In-Memory-Computing 3D-NAND Flash Supporting Similar-Vector-Matching
Operations on Edge-AI Devices},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {138--140},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731775},
doi = {10.1109/ISSCC42614.2022.9731775},
timestamp = {Wed, 04 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/HuWCLLWLLHHLC0L22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChiuYTHCWCHLLCP22,
author = {Yen{-}Cheng Chiu and
Chia{-}Sheng Yang and
Shih{-}Hsih Teng and
Hsiao{-}Yu Huang and
Fu{-}Chun Chang and
Yuan Wu and
Yu{-}An Chien and
Fang{-}Ling Hsieh and
Chung{-}Yuan Li and
Guan{-}Yi Lin and
Po{-}Jung Chen and
Tsen{-}Hsiang Pan and
Chung{-}Chuan Lo and
Win{-}San Khwa and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Chieh{-}Pu Lo and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {A 22nm 4Mb {STT-MRAM} Data-Encrypted Near-Memory Computation Macro
with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b
{MAC} for {AI} Operations},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {178--180},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731621},
doi = {10.1109/ISSCC42614.2022.9731621},
timestamp = {Tue, 20 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/ChiuYTHCWCHLLCP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/HuW0LLWLHLSHHLC22,
author = {Han{-}Wen Hu and
Wei{-}Chen Wang and
Yuan{-}Hao Chang and
Yung{-}Chun Lee and
Bo{-}Rong Lin and
Huai{-}Mu Wang and
Yen{-}Po Lin and
Yu{-}Ming Huang and
Chong{-}Ying Lee and
Tzu{-}Hsiang Su and
Chih{-}Chang Hsieh and
Chia{-}Ming Hu and
Yi{-}Ting Lai and
Chung Kuang Chen and
Han{-}Sung Chen and
Hsiang{-}Pang Li and
Tei{-}Wei Kuo and
Meng{-}Fan Chang and
Keh{-}Chung Wang and
Chun{-}Hsiung Hung and
Chih{-}Yuan Lu},
title = {{ICE:} An Intelligent Cognition Engine with 3D NAND-based In-Memory
Computing for Vector Similarity Search Acceleration},
booktitle = {55th {IEEE/ACM} International Symposium on Microarchitecture, {MICRO}
2022, Chicago, IL, USA, October 1-5, 2022},
pages = {763--783},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MICRO56248.2022.00058},
doi = {10.1109/MICRO56248.2022.00058},
timestamp = {Wed, 04 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/micro/HuW0LLWLHLSHHLC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HsuCLLTCH21,
author = {Tzu{-}Hsiang Hsu and
Yi{-}Ren Chen and
Ren{-}Shuo Liu and
Chung{-}Chuan Lo and
Kea{-}Tiong Tang and
Meng{-}Fan Chang and
Chih{-}Cheng Hsieh},
title = {A 0.5-V Real-Time Computational {CMOS} Image Sensor With Programmable
Kernel for Feature Extraction},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {5},
pages = {1588--1596},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2020.3034192},
doi = {10.1109/JSSC.2020.3034192},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/HsuCLLTCH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/LinPGTWCLSYCQW21,
author = {Bohan Lin and
Yachuan Pang and
Bin Gao and
Jianshi Tang and
Dong Wu and
Ting{-}Wei Chang and
Wei{-}En Lin and
Xiaoyu Sun and
Shimeng Yu and
Meng{-}Fan Chang and
He Qian and
Huaqiang Wu},
title = {A Highly Reliable {RRAM} Physically Unclonable Function Utilizing
Post-Process Randomness Source},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {5},
pages = {1641--1650},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2021.3050295},
doi = {10.1109/JSSC.2021.3050295},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/LinPGTWCLSYCQW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/YueLLSYTCRWCLY21,
author = {Jinshan Yue and
Yongpan Liu and
Ruoyang Liu and
Wenyu Sun and
Zhe Yuan and
Yung{-}Ning Tu and
Yi{-}Ju Chen and
Ao Ren and
Yanzhi Wang and
Meng{-}Fan Chang and
Xueqing Li and
Huazhong Yang},
title = {{STICKER-T:} An Energy-Efficient Neural Network Processor Using Block-Circulant
Algorithm and Unified Frequency-Domain Acceleration},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {6},
pages = {1936--1948},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2020.3030264},
doi = {10.1109/JSSC.2020.3030264},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/YueLLSYTCRWCLY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HsuCCCLLTCH21,
author = {Tzu{-}Hsiang Hsu and
Yen{-}Kai Chen and
Min{-}Yang Chiu and
Guan{-}Cheng Chen and
Ren{-}Shuo Liu and
Chung{-}Chuan Lo and
Kea{-}Tiong Tang and
Meng{-}Fan Chang and
Chih{-}Cheng Hsieh},
title = {A 0.8 {V} Multimode Vision Sensor for Motion and Saliency Detection
With Ping-Pong {PWM} Pixel},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {8},
pages = {2516--2524},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2021.3075746},
doi = {10.1109/JSSC.2021.3075746},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/HsuCCCLLTCH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SiTHSLWLWLCCSLL21,
author = {Xin Si and
Yung{-}Ning Tu and
Wei{-}Hsing Huang and
Jian{-}Wei Su and
Pei{-}Jung Lu and
Jing{-}Hong Wang and
Ta{-}Wei Liu and
Ssu{-}Yen Wu and
Ruhui Liu and
Yen{-}Chi Chou and
Yen{-}Lin Chung and
William Shih and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Nan{-}Chun Lien and
Wei{-}Chiang Shih and
Yajuan He and
Qiang Li and
Meng{-}Fan Chang},
title = {A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro
With 8-b {MAC} Operation for Edge {AI} Chips},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {9},
pages = {2817--2831},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2021.3073254},
doi = {10.1109/JSSC.2021.3073254},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SiTHSLWLWLCCSLL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pieee/XiGTCCHSQW21,
author = {Yue Xi and
Bin Gao and
Jianshi Tang and
An Chen and
Meng{-}Fan Chang and
Xiaobo Sharon Hu and
Jan Van der Spiegel and
He Qian and
Huaqiang Wu},
title = {In-memory Learning with Analog Resistive Switching Memory: {A} Review
and Perspective},
journal = {Proc. {IEEE}},
volume = {109},
number = {1},
pages = {14--42},
year = {2021},
url = {https://doi.org/10.1109/JPROC.2020.3004543},
doi = {10.1109/JPROC.2020.3004543},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/pieee/XiGTCCHSQW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/JhangXHCC21,
author = {Chuan{-}Jia Jhang and
Cheng{-}Xin Xue and
Je{-}Min Hung and
Fu{-}Chun Chang and
Meng{-}Fan Chang},
title = {Challenges and Trends of SRAM-Based Computing-In-Memory for {AI} Edge
Devices},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {68},
number = {5},
pages = {1773--1786},
year = {2021},
url = {https://doi.org/10.1109/TCSI.2021.3064189},
doi = {10.1109/TCSI.2021.3064189},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasI/JhangXHCC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasII/WangYDSXLSGZLCL21,
author = {Linfang Wang and
Wang Ye and
Chunmeng Dou and
Xin Si and
Xiaoxin Xu and
Jing Liu and
Dashan Shang and
Jianfeng Gao and
Feng Zhang and
Yongpan Liu and
Meng{-}Fan Chang and
Qi Liu},
title = {Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage
Division in 2T2R {RRAM} With Input-Dependent Sensing Control},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {68},
number = {5},
pages = {1640--1644},
year = {2021},
url = {https://doi.org/10.1109/TCSII.2021.3067385},
doi = {10.1109/TCSII.2021.3067385},
timestamp = {Fri, 12 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasII/WangYDSXLSGZLCL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/SiZYC21,
author = {Xin Si and
Yongliang Zhou and
Jun Yang and
Meng{-}Fan Chang},
editor = {Fan Ye and
Ting{-}Ao Tang},
title = {Challenge and Trend of {SRAM} Based Computation-in-Memory Circuits
for {AI} Edge Devices},
booktitle = {14th {IEEE} International Conference on ASIC, {ASICON} 2021, Kunming,
China, October 26-29, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ASICON52560.2021.9620429},
doi = {10.1109/ASICON52560.2021.9620429},
timestamp = {Mon, 06 Dec 2021 11:20:15 +0100},
biburl = {https://dblp.org/rec/conf/asicon/SiZYC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/YoonCKCCR21,
author = {Jong{-}Hyeok Yoon and
Muya Chang and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory {RRAM} Macro
with Voltage-sensing Read and Write Verification for reliable multi-bit
{RRAM} operation},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2021, Austin,
TX, USA, April 25-30, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/CICC51472.2021.9431412},
doi = {10.1109/CICC51472.2021.9431412},
timestamp = {Thu, 20 May 2021 14:06:55 +0200},
biburl = {https://dblp.org/rec/conf/cicc/YoonCKCCR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WangYADLCL21,
author = {Linfang Wang and
Wang Ye and
Junjie An and
Chunmeng Dou and
Qi Liu and
Meng{-}Fan Chang and
Ming Liu},
title = {Sparsity-Aware Clamping Readout Scheme for High Parallelism and Low
Power Nonvolatile Computing-in-Memory Based on Resistive Memory},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
Daegu, South Korea, May 22-28, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCAS51556.2021.9401670},
doi = {10.1109/ISCAS51556.2021.9401670},
timestamp = {Wed, 25 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/WangYADLCL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhangZZQWLZHDSC21,
author = {Yuxin Zhang and
Sitao Zeng and
Zhiguo Zhu and
Zhaolong Qin and
Chen Wang and
Jingjing Li and
Sanfeng Zhang and
Yajuan He and
Chunmeng Dou and
Xin Si and
Meng{-}Fan Chang and
Qiang Li},
title = {A 40nm 1Mb 35.6 {TOPS/W} {MLC} NOR-Flash Based Computation-in-Memory
Structure for Machine Learning},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
Daegu, South Korea, May 22-28, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCAS51556.2021.9401600},
doi = {10.1109/ISCAS51556.2021.9401600},
timestamp = {Wed, 25 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ZhangZZQWLZHDSC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/YueFHHWYZLSCWHC21,
author = {Jinshan Yue and
Xiaoyu Feng and
Yifan He and
Yuxuan Huang and
Yipeng Wang and
Zhe Yuan and
Mingtao Zhan and
Jiaxin Liu and
Jian{-}Wei Su and
Yen{-}Lin Chung and
Ping{-}Chun Wu and
Li{-}Yang Hung and
Meng{-}Fan Chang and
Nan Sun and
Xueqing Li and
Huazhong Yang and
Yongpan Liu},
title = {A 2.75-to-75.9TOPS/W Computing-in-Memory {NN} Processor Supporting
Set-Associate Block-Wise Zero Skipping and Ping-Pong {CIM} with Simultaneous
Computation and Weight Updating},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {238--240},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365958},
doi = {10.1109/ISSCC42613.2021.9365958},
timestamp = {Mon, 25 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/YueFHHWYZLSCWHC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/GuoYSHLTWLCLWY21,
author = {Ruiqi Guo and
Zhiheng Yue and
Xin Si and
Te Hu and
Hao Li and
Limei Tang and
Yabing Wang and
Leibo Liu and
Meng{-}Fan Chang and
Qiang Li and
Shaojun Wei and
Shouyi Yin},
title = {15.4 {A} 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor
Using Bit-Level-Sparsity-Based Optimization and Variable-Precision
Quantization},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {242--244},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365989},
doi = {10.1109/ISSCC42613.2021.9365989},
timestamp = {Wed, 25 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/GuoYSHLTWLCLWY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangHB21,
author = {Meng{-}Fan Chang and
Ru Huang and
Seung{-}Jun Bae},
title = {Session 16 Overview: Computation in Memory Memory Subcommittee},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {244--245},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365967},
doi = {10.1109/ISSCC42613.2021.9365967},
timestamp = {Wed, 10 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/ChangHB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/XueHKHHCCLJSKLL21,
author = {Cheng{-}Xin Xue and
Je{-}Min Hung and
Hui{-}Yao Kao and
Yen{-}Hsiang Huang and
Sheng{-}Po Huang and
Fu{-}Chun Chang and
Peng Chen and
Ta{-}Wei Liu and
Chuan{-}Jia Jhang and
Chin{-}I Su and
Win{-}San Khwa and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91
to 195.7TOPS/W for Tiny {AI} Edge Devices},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {245--247},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365769},
doi = {10.1109/ISSCC42613.2021.9365769},
timestamp = {Wed, 10 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/XueHKHHCCLJSKLL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SuCLLLWCHRPLCSL21,
author = {Jian{-}Wei Su and
Yen{-}Chi Chou and
Ruhui Liu and
Ta{-}Wei Liu and
Pei{-}Jung Lu and
Ping{-}Chun Wu and
Yen{-}Lin Chung and
Li{-}Yang Hung and
Jin{-}Sheng Ren and
Tianlong Pan and
Sih{-}Han Li and
Shih{-}Chieh Chang and
Shyh{-}Shyuan Sheu and
Wei{-}Chung Lo and
Chih{-}I Wu and
Xin Si and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Meng{-}Fan Chang},
title = {16.3 {A} 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision
for {AI} Edge Chips},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {250--252},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365984},
doi = {10.1109/ISSCC42613.2021.9365984},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/SuCLLLWCHRPLCSL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChihLFSLNCLLMZS21,
author = {Yu{-}Der Chih and
Po{-}Hao Lee and
Hidehiro Fujiwara and
Yi{-}Chun Shih and
Chia{-}Fu Lee and
Rawan Naous and
Yu{-}Lin Chen and
Chieh{-}Pu Lo and
Cheng{-}Han Lu and
Haruki Mori and
Wei{-}Cheng Zhao and
Dar Sun and
Mahmut E. Sinangil and
Yen{-}Huei Chen and
Tan{-}Li Chou and
Kerem Akarvardar and
Hung{-}Jen Liao and
Yih Wang and
Meng{-}Fan Chang and
Tsung{-}Yung Jonathan Chang},
title = {An 89TOPS/W and 16.3TOPS/mm\({}^{\mbox{2}}\) All-Digital SRAM-Based
Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning
Edge Applications},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {252--254},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365766},
doi = {10.1109/ISSCC42613.2021.9365766},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChihLFSLNCLLMZS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/YoonCKCCR21,
author = {Jong{-}Hyeok Yoon and
Muya Chang and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {29.1 {A} 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital
{RRAM} Macro with Active-Feedback-Based Read and In-Situ Write Verification},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {404--406},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365926},
doi = {10.1109/ISSCC42613.2021.9365926},
timestamp = {Wed, 10 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/YoonCKCCR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/GiordanoPKRGDKK21,
author = {Massimo Giordano and
Kartik Prabhu and
Kalhan Koul and
Robert M. Radway and
Albert Gural and
Rohan Doshi and
Zainab F. Khan and
John W. Kustin and
Timothy Liu and
Gregorio B. Lopes and
Victor Turbiner and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Gu{\'{e}}nol{\'{e}} Lallement and
Boris Murmann and
Subhasish Mitra and
Priyanka Raina},
title = {{CHIMERA:} {A} 0.92 TOPS, 2.2 {TOPS/W} Edge {AI} Accelerator with
2 MByte On-Chip Foundry Resistive {RAM} for Efficient Training and
Inference},
booktitle = {2021 Symposium on {VLSI} Circuits, Kyoto, Japan, June 13-19, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/VLSICircuits52068.2021.9492347},
doi = {10.23919/VLSICIRCUITS52068.2021.9492347},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/GiordanoPKRGDKK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/GuoLLZTSLCWY21,
author = {Ruiqi Guo and
Hao Li and
Ruhui Liu and
Zhixiao Zhang and
Limei Tang and
Hao Sun and
Leibo Liu and
Meng{-}Fan Chang and
Shaojun Wei and
Shouyi Yin},
title = {A 6.54-to-26.03 {TOPS/W} Computing-In-Memory {RNN} Processor using
Input Similarity Optimization and Attention-based Context-breaking
with Output Speculation},
booktitle = {2021 Symposium on {VLSI} Circuits, Kyoto, Japan, June 13-19, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/VLSICircuits52068.2021.9492492},
doi = {10.23919/VLSICIRCUITS52068.2021.9492492},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/GuoLLZTSLCWY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/CarusoneSCC20,
author = {Tony Chan Carusone and
Mingoo Seok and
Hsie{-}Chia Chang and
Meng{-}Fan Chang},
title = {Introduction to the Special Issue on the 2019 {IEEE} International
Solid-State Circuits Conference {(ISSCC)}},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {1},
pages = {3--5},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2019.2953371},
doi = {10.1109/JSSC.2019.2953371},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/CarusoneSCC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SiLYLHTLCCTHWCW20,
author = {Xin Si and
Rui Liu and
Shimeng Yu and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Qiang Li and
Meng{-}Fan Chang and
Jia{-}Jing Chen and
Yung{-}Ning Tu and
Wei{-}Hsing Huang and
Jing{-}Hong Wang and
Yen{-}Cheng Chiu and
Wei{-}Chen Wei and
Ssu{-}Yen Wu and
Xiaoyu Sun},
title = {A Twin-8T {SRAM} Computation-in-Memory Unit-Macro for Multibit CNN-Based
{AI} Edge Processors},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {1},
pages = {189--202},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2019.2952773},
doi = {10.1109/JSSC.2019.2952773},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SiLYLHTLCCTHWCW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/XueCCKCLKLLHTCC20,
author = {Cheng{-}Xin Xue and
Ting{-}Wei Chang and
Tung{-}Cheng Chang and
Hui{-}Yao Kao and
Yen{-}Cheng Chiu and
Chun{-}Ying Lee and
Ya{-}Chin King and
Chrong Jung Lin and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Wei{-}Hao Chen and
Meng{-}Fan Chang and
Je{-}Syu Liu and
Jia{-}Fang Li and
Wei{-}Yu Lin and
Wei{-}En Lin and
Jing{-}Hong Wang and
Wei{-}Chen Wei and
Tsung{-}Yuan Huang},
title = {Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit
Input and Weight for CNN-Based {AI} Edge Processors},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {1},
pages = {203--215},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2019.2951363},
doi = {10.1109/JSSC.2019.2951363},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/XueCCKCLKLLHTCC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChiuZCSLTSHWWHS20,
author = {Yen{-}Cheng Chiu and
Zhixiao Zhang and
Jia{-}Jing Chen and
Xin Si and
Ruhui Liu and
Yung{-}Ning Tu and
Jian{-}Wei Su and
Wei{-}Hsing Huang and
Jing{-}Hong Wang and
Wei{-}Chen Wei and
Je{-}Min Hung and
Shyh{-}Shyuan Sheu and
Sih{-}Han Li and
Chih{-}I Wu and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Meng{-}Fan Chang},
title = {A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory
Unit-Macro for CNN-Based {AI} Edge Processors},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {10},
pages = {2790--2801},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2020.3005754},
doi = {10.1109/JSSC.2020.3005754},
timestamp = {Tue, 06 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChiuZCSLTSHWWHS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/JiangHPSCHLLCY20,
author = {Hongwu Jiang and
Shanshi Huang and
Xiaochen Peng and
Jian{-}Wei Su and
Yen{-}Chi Chou and
Wei{-}Hsing Huang and
Ta{-}Wei Liu and
Ruhui Liu and
Meng{-}Fan Chang and
Shimeng Yu},
title = {A Two-way {SRAM} Array based Accelerator for Deep Neural Network On-chip
Training},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218524},
doi = {10.1109/DAC18072.2020.9218524},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/JiangHPSCHLLCY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HsuCWTWYSCLLTCH20,
author = {Tzu{-}Hsiang Hsu and
Yen{-}Kai Chen and
Jun{-}Shen Wu and
Wen{-}Chien Ting and
Cheng{-}Te Wang and
Chen{-}Fu Yeh and
Syuan{-}Hao Sie and
Yi{-}Ren Chen and
Ren{-}Shuo Liu and
Chung{-}Chuan Lo and
Kea{-}Tiong Tang and
Meng{-}Fan Chang and
Chih{-}Cheng Hsieh},
title = {5.9 {A} 0.8V Multimode Vision Sensor for Motion and Saliency Detection
with Ping-Pong {PWM} Pixel},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {110--112},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062926},
doi = {10.1109/ISSCC19947.2020.9062926},
timestamp = {Sat, 18 Apr 2020 17:41:44 +0200},
biburl = {https://dblp.org/rec/conf/isscc/HsuCWTWYSCLLTCH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangCLHCXWKCHT20,
author = {Tung{-}Cheng Chang and
Yen{-}Cheng Chiu and
Chun{-}Ying Lee and
Je{-}Min Hung and
Kuang{-}Tang Chang and
Cheng{-}Xin Xue and
Ssu{-}Yen Wu and
Hui{-}Yao Kao and
Peng Chen and
Hsiao{-}Yu Huang and
Shih{-}Hsih Teng and
Meng{-}Fan Chang},
title = {13.4 {A} 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode {STT-MRAM}
Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {224--226},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9063072},
doi = {10.1109/ISSCC19947.2020.9063072},
timestamp = {Sat, 18 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChangCLHCXWKCHT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/YueYFHZSLCLYL20,
author = {Jinshan Yue and
Zhe Yuan and
Xiaoyu Feng and
Yifan He and
Zhixiao Zhang and
Xin Si and
Ruhui Liu and
Meng{-}Fan Chang and
Xueqing Li and
Huazhong Yang and
Yongpan Liu},
title = {14.3 {A} 65nm Computing-in-Memory-Based {CNN} Processor with 2.9-to-35.8TOPS/W
System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling
Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {234--236},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062958},
doi = {10.1109/ISSCC19947.2020.9062958},
timestamp = {Sat, 18 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/YueYFHZSLCLYL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SuSCCHTLLLWZJHL20,
author = {Jian{-}Wei Su and
Xin Si and
Yen{-}Chi Chou and
Ting{-}Wei Chang and
Wei{-}Hsing Huang and
Yung{-}Ning Tu and
Ruhui Liu and
Pei{-}Jung Lu and
Ta{-}Wei Liu and
Jing{-}Hong Wang and
Zhixiao Zhang and
Hongwu Jiang and
Shanshi Huang and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Shyh{-}Shyuan Sheu and
Sih{-}Han Li and
Heng{-}Yuan Lee and
Shih{-}Chieh Chang and
Shimeng Yu and
Meng{-}Fan Chang},
title = {15.2 {A} 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T
{SRAM} Compute-in-Memory Macro for {AI} Edge Chips},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {240--242},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062949},
doi = {10.1109/ISSCC19947.2020.9062949},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/SuSCCHTLLLWZJHL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/XueHLCKWLWHWCHC20,
author = {Cheng{-}Xin Xue and
Tsung{-}Yuan Huang and
Je{-}Syu Liu and
Ting{-}Wei Chang and
Hui{-}Yao Kao and
Jing{-}Hong Wang and
Ta{-}Wei Liu and
Shih{-}Ying Wei and
Sheng{-}Po Huang and
Wei{-}Chen Wei and
Yi{-}Ren Chen and
Tzu{-}Hsiang Hsu and
Yen{-}Kai Chen and
Yun{-}Chen Lo and
Tai{-}Hsing Wen and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Meng{-}Fan Chang},
title = {15.4 {A} 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W
for Multibit {MAC} Computing for Tiny {AI} Edge Devices},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {244--246},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9063078},
doi = {10.1109/ISSCC19947.2020.9063078},
timestamp = {Sat, 18 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/XueHLCKWLWHWCHC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SiTHSLWLWLCZSWL20,
author = {Xin Si and
Yung{-}Ning Tu and
Wei{-}Hsing Huang and
Jian{-}Wei Su and
Pei{-}Jung Lu and
Jing{-}Hong Wang and
Ta{-}Wei Liu and
Ssu{-}Yen Wu and
Ruhui Liu and
Yen{-}Chi Chou and
Zhixiao Zhang and
Syuan{-}Hao Sie and
Wei{-}Chen Wei and
Yun{-}Chen Lo and
Tai{-}Hsing Wen and
Tzu{-}Hsiang Hsu and
Yen{-}Kai Chen and
William Shih and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Nan{-}Chun Lien and
Wei{-}Chiang Shih and
Yajuan He and
Qiang Li and
Meng{-}Fan Chang},
title = {15.5 {A} 28nm 64Kb 6T {SRAM} Computing-in-Memory Macro with 8b {MAC}
Operation for {AI} Edge Chips},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {246--248},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062995},
doi = {10.1109/ISSCC19947.2020.9062995},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/SiTHSLWLWLCZSWL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/Liu0YWCPZLXCTWC20,
author = {Qi Liu and
Bin Gao and
Peng Yao and
Dong Wu and
Junren Chen and
Yachuan Pang and
Wenqiang Zhang and
Yan Liao and
Cheng{-}Xin Xue and
Wei{-}Hao Chen and
Jianshi Tang and
Yu Wang and
Meng{-}Fan Chang and
He Qian and
Huaqiang Wu},
title = {33.2 {A} Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory
Chip with Fully Parallel {MAC} Computing},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {500--502},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062953},
doi = {10.1109/ISSCC19947.2020.9062953},
timestamp = {Wed, 25 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/Liu0YWCPZLXCTWC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/YangXXL0ZC020,
author = {Jianguo Yang and
Xiaoyong Xue and
Xiaoxin Xu and
Hangbing Lv and
Feng Zhang and
Xiaoyang Zeng and
Meng{-}Fan Chang and
Ming Liu},
title = {A 28nm 1.5Mb Embedded 1T2R {RRAM} with 14.8 Mb/mm\({}^{\mbox{2}}\)
using Sneaking Current Suppression and Compensation Techniques},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9163035},
doi = {10.1109/VLSICIRCUITS18222.2020.9163035},
timestamp = {Mon, 24 Aug 2020 16:22:01 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/YangXXL0ZC020.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2010-12861,
author = {Syuan{-}Hao Sie and
Jye{-}Luen Lee and
Yi{-}Ren Chen and
Chih{-}Cheng Lu and
Chih{-}Cheng Hsieh and
Meng{-}Fan Chang and
Kea{-}Tiong Tang},
title = {{MARS:} Multi-macro Architecture {SRAM} CIM-Based Accelerator with
Co-designed Compressed Neural Networks},
journal = {CoRR},
volume = {abs/2010.12861},
year = {2020},
url = {https://arxiv.org/abs/2010.12861},
eprinttype = {arXiv},
eprint = {2010.12861},
timestamp = {Mon, 02 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2010-12861.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/aisy/YanLQXCCL19,
author = {Bonan Yan and
Bing Li and
Ximing Qiao and
Cheng{-}Xin Xue and
Meng{-}Fan Chang and
Yiran Chen and
Hai Helen Li},
title = {Resistive Memory-Based In-Memory Computing: From Device and Large-Scale
Integration System Perspectives},
journal = {Adv. Intell. Syst.},
volume = {1},
number = {7},
pages = {1900068},
year = {2019},
url = {https://doi.org/10.1002/aisy.201900068},
doi = {10.1002/AISY.201900068},
timestamp = {Sat, 28 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/aisy/YanLQXCCL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/LoLLLYCKLCCC19,
author = {Chieh{-}Pu Lo and
Wen{-}Zhang Lin and
Wei{-}Yu Lin and
Huan{-}Ting Lin and
Tzu{-}Hsien Yang and
Yen{-}Ning Chiang and
Ya{-}Chin King and
Chrong Jung Lin and
Yu{-}Der Chih and
Tsung{-}Yung Jonathon Chang and
Meng{-}Fan Chang},
title = {A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode
Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against
Resistance and Write-Delay Variation},
journal = {{IEEE} J. Solid State Circuits},
volume = {54},
number = {2},
pages = {584--595},
year = {2019},
url = {https://doi.org/10.1109/JSSC.2018.2873588},
doi = {10.1109/JSSC.2018.2873588},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/LoLLLYCKLCCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/XueZYCYC19,
author = {Cheng{-}Xin Xue and
Wei{-}Cheng Zhao and
Tzu{-}Hsien Yang and
Yi{-}Ju Chen and
Hiroyuki Yamauchi and
Meng{-}Fan Chang},
title = {A 28-nm 320-Kb {TCAM} Macro Using Split-Controlled Single-Load 14T
Cell and Triple-Margin Voltage Sense Amplifier},
journal = {{IEEE} J. Solid State Circuits},
volume = {54},
number = {10},
pages = {2743--2753},
year = {2019},
url = {https://doi.org/10.1109/JSSC.2019.2915577},
doi = {10.1109/JSSC.2019.2915577},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/XueZYCYC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/ZhangSSRC19,
author = {Zhixiao Zhang and
Xin Si and
Srivatsa Srinivasa and
Akshay Krishna Ramanathan and
Meng{-}Fan Chang},
title = {Recent Advances in Compute-in-Memory Support for {SRAM} Using Monolithic
3-D Integration},
journal = {{IEEE} Micro},
volume = {39},
number = {6},
pages = {28--37},
year = {2019},
url = {https://doi.org/10.1109/MM.2019.2946489},
doi = {10.1109/MM.2019.2946489},
timestamp = {Fri, 27 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/micro/ZhangSSRC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/WangLSFWLLZWCL19,
author = {Yiming Wang and
Yun Li and
Haihua Shen and
Dongyu Fan and
Wei Wang and
Ling Li and
Qi Liu and
Feng Zhang and
Xinghua Wang and
Meng{-}Fan Chang and
Ming Liu},
title = {A Few-Step and Low-Cost Memristor Logic Based on {MIG} Logic for Frequent-Off
Instant-On Circuits in IoT Applications},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {66-II},
number = {4},
pages = {662--666},
year = {2019},
url = {https://doi.org/10.1109/TCSII.2018.2882388},
doi = {10.1109/TCSII.2018.2882388},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/WangLSFWLLZWCL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/SrinivasaRLCGCG19,
author = {Srivatsa Rangachar Srinivasa and
Akshay Krishna Ramanathan and
Xueqing Li and
Wei{-}Hao Chen and
Sumeet Kumar Gupta and
Meng{-}Fan Chang and
Swaroop Ghosh and
Jack Sampson and
Vijaykrishnan Narayanan},
title = {{ROBIN:} Monolithic-3D {SRAM} for Enhanced Robustness with In-Memory
Computation Support},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {66-I},
number = {7},
pages = {2533--2545},
year = {2019},
url = {https://doi.org/10.1109/TCSI.2019.2897497},
doi = {10.1109/TCSI.2019.2897497},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/SrinivasaRLCGCG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/SiKCLSLYYLC19,
author = {Xin Si and
Win{-}San Khwa and
Jia{-}Jing Chen and
Jia{-}Fang Li and
Xiaoyu Sun and
Rui Liu and
Shimeng Yu and
Hiroyuki Yamauchi and
Qiang Li and
Meng{-}Fan Chang},
title = {A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully
Parallel Product-Sum Operation for Binarized {DNN} Edge Processors},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {66-I},
number = {11},
pages = {4172--4185},
year = {2019},
url = {https://doi.org/10.1109/TCSI.2019.2928043},
doi = {10.1109/TCSI.2019.2928043},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/SiKCLSLYYLC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AliotoAABBCCCCC19,
author = {Massimo Alioto and
Magdy S. Abadir and
Tughrul Arslan and
Chirn Chye Boon and
Andreas Burg and
Chip{-}Hong Chang and
Meng{-}Fan Chang and
Yao{-}Wen Chang and
Poki Chen and
Pasquale Corsonello and
Paolo Crovetti and
Shiro Dosho and
Rolf Drechsler and
Ibrahim Abe M. Elfadel and
Ruonan Han and
Masanori Hashimoto and
Chun{-}Huat Heng and
Deukhyoun Heo and
Tsung{-}Yi Ho and
Houman Homayoun and
Yuh{-}Shyan Hwang and
Ajay Joshi and
Rajiv V. Joshi and
Tanay Karnik and
Chulwoo Kim and
Tony Tae{-}Hyoung Kim and
Jaydeep Kulkarni and
Volkan Kursun and
Yoonmyung Lee and
Hai Helen Li and
Huawei Li and
Prabhat Mishra and
Baker Mohammad and
Mehran Mozaffari Kermani and
Makoto Nagata and
Koji Nii and
Partha Pratim Pande and
Bipul C. Paul and
Vasilis F. Pavlidis and
Jos{\'{e}} Pineda de Gyvez and
Ioannis Savidis and
Patrick Schaumont and
Fabio Sebastiano and
Anirban Sengupta and
Mingoo Seok and
Mircea R. Stan and
Mark M. Tehranipoor and
Aida Todri{-}Sanial and
Marian Verhelst and
Valerio Vignoli and
Xiaoqing Wen and
Jiang Xu and
Wei Zhang and
Zhengya Zhang and
Jun Zhou and
Mark Zwolinski and
Stacey Weber},
title = {Editorial {TVLSI} Positioning - Continuing and Accelerating an Upward
Trajectory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {253--280},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2886389},
doi = {10.1109/TVLSI.2018.2886389},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AliotoAABBCCCCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/SiQCXSZLSLCW19,
author = {Xin Si and
He Qian and
Meng{-}Fan Chang and
Cheng{-}Xin Xue and
Jian{-}Wei Su and
Zhixiao Zhang and
Sih{-}Han Li and
Shyh{-}Shyuan Sheu and
Heng{-}Yuan Lee and
Ping{-}Cheng Chen and
Huaqiang Wu},
title = {Circuit Design Challenges in Computing-in-Memory for {AI} Edge Devices},
booktitle = {13th {IEEE} International Conference on ASIC, {ASICON} 2019, Chongqing,
China, October 29 - November 1, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ASICON47005.2019.8983627},
doi = {10.1109/ASICON47005.2019.8983627},
timestamp = {Wed, 12 Feb 2020 16:13:42 +0100},
biburl = {https://dblp.org/rec/conf/asicon/SiQCXSZLSLCW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/HsuCWWCCKCKLLTC19,
author = {Tzu{-}Hsiang Hsu and
Yen{-}Kai Chen and
Tai{-}Hsing Wen and
Wei{-}Chen Wei and
Yi{-}Ren Chen and
Fu{-}Chun Chang and
Ren{-}Shuo Liu and
Chung{-}Chuan Lo and
Kea{-}Tiong Tang and
Meng{-}Fan Chang and
Chih{-}Cheng Hsieh},
title = {A 0.5V Real-Time Computational {CMOS} Image Sensor with Programmable
Kernel for Always-On Feature Extraction},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2019, Macau,
SAR, China, November 4-6, 2019},
pages = {33--34},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/A-SSCC47793.2019.9056945},
doi = {10.1109/A-SSCC47793.2019.9056945},
timestamp = {Wed, 06 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/HsuCWWCCKCKLLTC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/ZhangCSTSHWWCHS19,
author = {Zhixiao Zhang and
Jia{-}Jing Chen and
Xin Si and
Yung{-}Ning Tu and
Jian{-}Wei Su and
Wei{-}Hsing Huang and
Jing{-}Hong Wang and
Wei{-}Chen Wei and
Yen{-}Cheng Chiu and
Je{-}Min Hong and
Shyh{-}Shyuan Sheu and
Sih{-}Han Li and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Meng{-}Fan Chang},
title = {A 55nm 1-to-8 bit Configurable 6T {SRAM} based Computing-in-Memory
Unit-Macro for CNN-based {AI} Edge Processors},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2019, Macau,
SAR, China, November 4-6, 2019},
pages = {217--218},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/A-SSCC47793.2019.9056933},
doi = {10.1109/A-SSCC47793.2019.9056933},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asscc/ZhangCSTSHWWCHS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SrinivasaCTCSN19,
author = {Srivatsa Rangachar Srinivasa and
Wei{-}Hao Chen and
Yung{-}Ning Tu and
Meng{-}Fan Chang and
Jack Sampson and
Vijaykrishnan Narayanan},
title = {Monolithic-3D Integration Augmented Design Techniques for Computing
in SRAMs},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702536},
doi = {10.1109/ISCAS.2019.8702536},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SrinivasaCTCSN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/XueC19,
author = {Cheng{-}Xin Xue and
Meng{-}Fan Chang},
title = {Challenges in Circuit Designs of Nonvolatile-memory based computing-in-memory
for {AI} Edge Devices},
booktitle = {2019 International SoC Design Conference, {ISOCC} 2019, Jeju, Korea
(South), October 6-9, 2019},
pages = {164--165},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISOCC47750.2019.9027656},
doi = {10.1109/ISOCC47750.2019.9027656},
timestamp = {Fri, 20 Mar 2020 08:51:45 +0100},
biburl = {https://dblp.org/rec/conf/isocc/XueC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/YueLSYWTCRWCLYL19,
author = {Jinshan Yue and
Ruoyang Liu and
Wenyu Sun and
Zhe Yuan and
Zhibo Wang and
Yung{-}Ning Tu and
Yi{-}Ju Chen and
Ao Ren and
Yanzhi Wang and
Meng{-}Fan Chang and
Xueqing Li and
Huazhong Yang and
Yongpan Liu},
title = {A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor
Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1
{\texttimes} Higher TOPS/mm\({}^{\mbox{2}}\)and 6T HBST-TRAM-Based
2D Data-Reuse Architecture},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {138--140},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662360},
doi = {10.1109/ISSCC.2019.8662360},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/YueLSYWTCRWCLYL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/XueCLLLLWWCCHKW19,
author = {Cheng{-}Xin Xue and
Wei{-}Hao Chen and
Je{-}Syu Liu and
Jia{-}Fang Li and
Wei{-}Yu Lin and
Wei{-}En Lin and
Jing{-}Hong Wang and
Wei{-}Chen Wei and
Ting{-}Wei Chang and
Tung{-}Cheng Chang and
Tsung{-}Yuan Huang and
Hui{-}Yao Kao and
Shih{-}Ying Wei and
Yen{-}Cheng Chiu and
Chun{-}Ying Lee and
Chung{-}Chuan Lo and
Ya{-}Chin King and
Chorng{-}Jung Lin and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Meng{-}Fan Chang},
title = {A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel
{MAC} Computing Time for {CNN} Based {AI} Edge Processors},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {388--390},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662395},
doi = {10.1109/ISSCC.2019.8662395},
timestamp = {Tue, 12 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/XueCLLLLWWCCHKW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SiCTHWCWWSLYLHT19,
author = {Xin Si and
Jia{-}Jing Chen and
Yung{-}Ning Tu and
Wei{-}Hsing Huang and
Jing{-}Hong Wang and
Yen{-}Cheng Chiu and
Wei{-}Chen Wei and
Ssu{-}Yen Wu and
Xiaoyu Sun and
Rui Liu and
Shimeng Yu and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Qiang Li and
Meng{-}Fan Chang},
title = {A Twin-8T {SRAM} Computation-In-Memory Macro for Multiple-Bit CNN-Based
Machine Learning},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {396--398},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662392},
doi = {10.1109/ISSCC.2019.8662392},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/SiCTHWCWWSLYLHT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/PangGWYLCCLSYQC19,
author = {Yachun Pang and
Bin Gao and
Dong Wu and
Shengyu Yi and
Qi Liu and
Wei{-}Hao Chen and
Ting{-}Wei Chang and
Wei{-}En Lin and
Xiaoyu Sun and
Shimeng Yu and
He Qian and
Meng{-}Fan Chang and
Huaqiang Wu},
title = {A Reconfigurable {RRAM} Physically Unclonable Function Utilizing Post-Process
Randomness Source With {\textless}6{\texttimes}10\({}^{\mbox{-6}}\)
Native Bit Error Rate},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {402--404},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662307},
doi = {10.1109/ISSCC.2019.8662307},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/PangGWYLCCLSYQC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/GuoLZWOKCCLLCWY19,
author = {Ruiqi Guo and
Yonggang Liu and
Shixuan Zheng and
Ssu{-}Yen Wu and
Peng Ouyang and
Win{-}San Khwa and
Xi Chen and
Jia{-}Jing Chen and
Xiudong Li and
Leibo Liu and
Meng{-}Fan Chang and
Shaojun Wei and
Shouyi Yin},
title = {A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor
using 16 Computing-in-Memory {SRAM} Macros in 65nm {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {120},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778028},
doi = {10.23919/VLSIC.2019.8778028},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/GuoLZWOKCCLLCWY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/TangWYHCXKWHLLH19,
author = {Kea{-}Tiong Tang and
Wei{-}Chen Wei and
Zuo{-}Wei Yeh and
Tzu{-}Hsiang Hsu and
Yen{-}Cheng Chiu and
Cheng{-}Xin Xue and
Yu{-}Chun Kuo and
Tai{-}Hsing Wen and
Mon{-}Shu Ho and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Meng{-}Fan Chang},
title = {Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor
Into Convolutional Neural Network Accelerators For Low-Power Edge
Devices},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {166},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778074},
doi = {10.23919/VLSIC.2019.8778074},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/TangWYHCXKWHLLH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/ZhangKZCZ18,
author = {He Zhang and
Wang Kang and
Youguang Zhang and
Meng{-}Fan Chang and
Weisheng Zhao},
title = {A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled
{STT-RAM}},
journal = {{IEEE} Access},
volume = {6},
pages = {64250--64260},
year = {2018},
url = {https://doi.org/10.1109/ACCESS.2018.2878012},
doi = {10.1109/ACCESS.2018.2878012},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/ZhangKZCZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/BasuCCKLS18,
author = {Arindam Basu and
Meng{-}Fan Chang and
Elisabetta Chicca and
Tanay Karnik and
Hai Helen Li and
Jae{-}sun Seo},
title = {Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices,
Circuit, Architectures and Algorithms},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {8},
number = {1},
pages = {1--5},
year = {2018},
url = {https://doi.org/10.1109/JETCAS.2018.2810399},
doi = {10.1109/JETCAS.2018.2810399},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esticas/BasuCCKLS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ChouCJCWYCCHCT18,
author = {Ting{-}I Chou and
Kwuang{-}Han Chang and
Jia{-}Yin Jhang and
Shih{-}Wen Chiu and
Guoxing Wang and
Chia{-}Hsiang Yang and
Herming Chiueh and
Hsin Chen and
Chih{-}Cheng Hsieh and
Meng{-}Fan Chang and
Kea{-}Tiong Tang},
title = {A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {65-II},
number = {10},
pages = {1365--1369},
year = {2018},
url = {https://doi.org/10.1109/TCSII.2018.2854588},
doi = {10.1109/TCSII.2018.2854588},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ChouCJCWYCCHCT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeLELCCAW18,
author = {Albert Lee and
Hochul Lee and
Farbod Ebrahimi and
Bonnie Lam and
Wei{-}Hao Chen and
Meng{-}Fan Chang and
Pedram Khalili Amiri and
Kang{-}Lung Wang},
title = {A Dual-Data Line Read Scheme for High-Speed Low-Energy Resistive Nonvolatile
Memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {2},
pages = {272--279},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2766150},
doi = {10.1109/TVLSI.2017.2766150},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeLELCCAW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SrinivasaLCSGN18,
author = {Srivatsa Rangachar Srinivasa and
Xueqing Li and
Meng{-}Fan Chang and
John Sampson and
Sumeet Kumar Gupta and
Vijaykrishnan Narayanan},
title = {Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access
Capability Using Sequential Monolithic 3-D Integration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {4},
pages = {671--683},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2787562},
doi = {10.1109/TVLSI.2017.2787562},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SrinivasaLCSGN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/XueZYCYC18,
author = {Cheng{-}Xin Xue and
Wei{-}Cheng Zhao and
Tzu{-}Hsien Yang and
Yi{-}Ju Chen and
Hiroyuki Yamauchi and
Meng{-}Fan Chang},
title = {A 28mn 320Kb {TCAM} Macro with Sub-0.8ns Search Time and 3.5+x Improvement
in Delay-Area-Energy Product using Split-Controlled Single-Load 14T
Cell},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2018, Tainan,
Taiwan, November 5-7, 2018},
pages = {127--128},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASSCC.2018.8579323},
doi = {10.1109/ASSCC.2018.8579323},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asscc/XueZYCYC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/biocas/LiYCHWLLHHLCT18,
author = {Pin{-}Yi Li and
Cheng{-}Han Yang and
Wei{-}Hao Chen and
Jian{-}Hao Huang and
Wei{-}Chen Wei and
Je{-}Syu Liu and
Wei{-}Yu Lin and
Tzu{-}Hsiang Hsu and
Chih{-}Cheng Hsieh and
Ren{-}Shuo Liu and
Meng{-}Fan Chang and
Kea{-}Tiong Tang},
title = {A Neuromorphic Computing System for Bitwise Neural Networks Based
on ReRAM Synaptic Array},
booktitle = {2018 {IEEE} Biomedical Circuits and Systems Conference, BioCAS 2018,
Cleveland, OH, USA, October 17-19, 2018},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/BIOCAS.2018.8584810},
doi = {10.1109/BIOCAS.2018.8584810},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/biocas/LiYCHWLLHHLCT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiuPSKSCLCY18,
author = {Rui Liu and
Xiaochen Peng and
Xiaoyu Sun and
Win{-}San Khwa and
Xin Si and
Jia{-}Jing Chen and
Jia{-}Fang Li and
Meng{-}Fan Chang and
Shimeng Yu},
title = {Parallelizing {SRAM} arrays with customized bit-cell for binary neural
networks},
booktitle = {Proceedings of the 55th Annual Design Automation Conference, {DAC}
2018, San Francisco, CA, USA, June 24-29, 2018},
pages = {21:1--21:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3195970.3196089},
doi = {10.1145/3195970.3196089},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/LiuPSKSCLCY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LinCLYTYHCLC18,
author = {Meng{-}Yao Lin and
Hsiang{-}Yun Cheng and
Wei{-}Ting Lin and
Tzu{-}Hsien Yang and
I{-}Ching Tseng and
Chia{-}Lin Yang and
Han{-}Wen Hu and
Hung{-}Sheng Chang and
Hsiang{-}Pang Li and
Meng{-}Fan Chang},
editor = {Iris Bahar},
title = {{DL-RSIM:} a simulation framework to enable reliable ReRAM-based accelerators
for deep learning},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018},
pages = {31},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3240765.3240800},
doi = {10.1145/3240765.3240800},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/LinCLYTYHCLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/YangWYCHYL18,
author = {Yixiong Yang and
Zhibo Wang and
Pei Yang and
Meng{-}Fan Chang and
Mon{-}Shu Ho and
Huazhong Yang and
Yongpan Liu},
title = {A 2-GHz Direct Digital Frequency Synthesizer Based on {LUT} and Rotation},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018,
27-30 May 2018, Florence, Italy},
pages = {1--5},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISCAS.2018.8351207},
doi = {10.1109/ISCAS.2018.8351207},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/YangWYCHYL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/SrinivasaRLCHYS18,
author = {Srivatsa Rangachar Srinivasa and
Akshay Krishna Ramanathan and
Xueqing Li and
Wei{-}Hao Chen and
Fu{-}Kuo Hsueh and
Chih{-}Chao Yang and
Chang{-}Hong Shen and
Jia{-}Min Shieh and
Sumeet Kumar Gupta and
Meng{-}Fan Marvin Chang and
Swaroop Ghosh and
Jack Sampson and
Vijaykrishnan Narayanan},
title = {A Monolithic-3D {SRAM} Design with Enhanced Robustness and In-Memory
Computation Support},
booktitle = {Proceedings of the International Symposium on Low Power Electronics
and Design, {ISLPED} 2018, Seattle, WA, USA, July 23-25, 2018},
pages = {34:1--34:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3218603.3218645},
doi = {10.1145/3218603.3218645},
timestamp = {Fri, 30 Nov 2018 02:24:56 +0100},
biburl = {https://dblp.org/rec/conf/islped/SrinivasaRLCHYS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/YangLCLLC18,
author = {Tzu{-}Hsien Yang and
Kai{-}Xiang Li and
Yen{-}Ning Chiang and
Wei{-}Yu Lin and
Huan{-}Ting Lin and
Meng{-}Fan Chang},
title = {A 28nm 32Kb embedded 2T2MTJ {STT-MRAM} macro with 1.3ns read-access
time for fast and reliable read applications},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {482--484},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310394},
doi = {10.1109/ISSCC.2018.8310394},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/YangLCLLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChenLLHLYXYCCHK18,
author = {Wei{-}Hao Chen and
Kai{-}Xiang Li and
Wei{-}Yu Lin and
Kuo{-}Hsiang Hsu and
Pin{-}Yi Li and
Cheng{-}Han Yang and
Cheng{-}Xin Xue and
En{-}Yu Yang and
Yen{-}Kai Chen and
Yun{-}Sheng Chang and
Tzu{-}Hsiang Hsu and
Ya{-}Chin King and
Chorng{-}Jung Lin and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Meng{-}Fan Chang},
title = {A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns
multiply-and-accumulate for binary {DNN} {AI} edge processors},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {494--496},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310400},
doi = {10.1109/ISSCC.2018.8310400},
timestamp = {Wed, 14 Mar 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/ChenLLHLYXYCCHK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KhwaCLSYSLCLYC18,
author = {Win{-}San Khwa and
Jia{-}Jing Chen and
Jia{-}Fang Li and
Xin Si and
En{-}Yu Yang and
Xiaoyu Sun and
Rui Liu and
Pai{-}Yu Chen and
Qiang Li and
Shimeng Yu and
Meng{-}Fan Chang},
title = {A 65nm 4Kb algorithm-dependent computing-in-memory {SRAM} unit-macro
with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for
binary {DNN} edge processors},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {496--498},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310401},
doi = {10.1109/ISSCC.2018.8310401},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KhwaCLSYSLCLYC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/YuanYYW0YGLCYL18,
author = {Zhe Yuan and
Jinshan Yue and
Huanrui Yang and
Zhibo Wang and
Jinyang Li and
Yixiong Yang and
Qingwei Guo and
Xueqing Li and
Meng{-}Fan Chang and
Huazhong Yang and
Yongpan Liu},
title = {Sticker: {A} 0.41-62.1 {TOPS/W} 8Bit Neural Network Processor with
Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration
for Fully Connected Layers},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {33--34},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502404},
doi = {10.1109/VLSIC.2018.8502404},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/YuanYYW0YGLCYL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1803-05006,
author = {Albert Lee and
Bonnie Lam and
Wenyuan Li and
Hochul Lee and
Wei{-}Hao Chen and
Meng{-}Fan Chang and
Kang{-}L. Wang},
title = {Conditional Activation for Diverse Neurons in Heterogeneous Networks},
journal = {CoRR},
volume = {abs/1803.05006},
year = {2018},
url = {http://arxiv.org/abs/1803.05006},
eprinttype = {arXiv},
eprint = {1803.05006},
timestamp = {Fri, 21 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1803-05006.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KhwaCWLSYCWLBKL17,
author = {Win{-}San Khwa and
Meng{-}Fan Chang and
Jau{-}Yi Wu and
Ming{-}Hsiu Lee and
Tzu{-}Hsiang Su and
Keng{-}Hao Yang and
Tien{-}Fu Chen and
Tien{-}Yen Wang and
Hsiang{-}Pang Li and
Matthew J. BrightSky and
SangBum Kim and
Hsiang{-}Lam Lung and
Chung Lam},
title = {A Resistance Drift Compensation Scheme to Reduce {MLC} {PCM} Raw {BER}
by Over 100{\texttimes} for Storage Class Memory Applications},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {1},
pages = {218--228},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2016.2597822},
doi = {10.1109/JSSC.2016.2597822},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KhwaCWLSYCWLBKL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangLLCKYTCS17,
author = {Meng{-}Fan Chang and
Chien{-}Chen Lin and
Albert Lee and
Yen{-}Ning Chiang and
Chia{-}Chen Kuo and
Geng{-}Hau Yang and
Hsiang{-}Jen Tsai and
Tien{-}Fu Chen and
Shyh{-}Shyuan Sheu},
title = {A 3T1R Nonvolatile {TCAM} Using {MLC} ReRAM for Frequent-Off Instant-On
Filters in IoT and Big-Data Processing},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {6},
pages = {1664--1679},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2017.2681458},
doi = {10.1109/JSSC.2017.2681458},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChangLLCKYTCS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/LeeLLCHWSYWKLLA17,
author = {Albert Lee and
Chieh{-}Pu Lo and
Chien{-}Chen Lin and
Wei{-}Hao Chen and
Kuo{-}Hsiang Hsu and
Zhibo Wang and
Fang Su and
Zhe Yuan and
Qi Wei and
Ya{-}Chin King and
Chrong Jung Lin and
Hochul Lee and
Pedram Khalili Amiri and
Kang{-}Lung Wang and
Yu Wang and
Huazhong Yang and
Yongpan Liu and
Meng{-}Fan Chang},
title = {A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme
for Frequent-OFF Fast-Wake-Up Nonvolatile Processors},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {8},
pages = {2194--2207},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2017.2700788},
doi = {10.1109/JSSC.2017.2700788},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/LeeLLCHWSYWKLLA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangCCSWCY17,
author = {Meng{-}Fan Chang and
Chien{-}Fu Chen and
Ting{-}Hao Chang and
Chi{-}Chang Shuai and
Yen{-}Yao Wang and
Yi{-}Ju Chen and
Hiroyuki Yamauchi},
title = {A Compact-Area Low-VDDmin 6T {SRAM} With Improvement in Cell Stability,
Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {9},
pages = {2498--2514},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2017.2701547},
doi = {10.1109/JSSC.2017.2701547},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChangCCSWCY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WangLLSLYLLCCLK17,
author = {Zhibo Wang and
Yongpan Liu and
Albert Lee and
Fang Su and
Chieh{-}Pu Lo and
Zhe Yuan and
Jinyang Li and
Chien{-}Chen Lin and
Wei{-}Hao Chen and
Hsiao{-}Yun Chiu and
Wei{-}En Lin and
Ya{-}Chin King and
Chrong Jung Lin and
Pedram Khalili Amiri and
Kang{-}Lung Wang and
Meng{-}Fan Chang and
Huazhong Yang},
title = {A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain
Adaption and Self-Write-Termination Achieving {\textgreater} 4{\texttimes}
Faster Clock Frequency and {\textgreater} 6{\texttimes} Higher Restore
Speed},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {10},
pages = {2769--2785},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2017.2724024},
doi = {10.1109/JSSC.2017.2724024},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/WangLLSLYLLCCLK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuYLZZXSCY17,
author = {Yongpan Liu and
Jinshan Yue and
Hehe Li and
Qinghang Zhao and
Mengying Zhao and
Chun Jason Xue and
Guangyu Sun and
Meng{-}Fan Chang and
Huazhong Yang},
title = {Data Backup Optimization for Nonvolatile {SRAM} in Energy Harvesting
Sensor Nodes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {36},
number = {10},
pages = {1660--1673},
year = {2017},
url = {https://doi.org/10.1109/TCAD.2017.2648841},
doi = {10.1109/TCAD.2017.2648841},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuYLZZXSCY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/YangTLJCC17,
author = {Keng{-}Hao Yang and
Hsiang{-}Jen Tsai and
Chia{-}Yin Li and
Paul Jendra and
Meng{-}Fan Chang and
Tien{-}Fu Chen},
title = {eTag: Tag-Comparison in Memory to Achieve Direct Data Access based
on eDRAM to Improve Energy Efficiency of {DRAM} Cache},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {64-I},
number = {4},
pages = {858--868},
year = {2017},
url = {https://doi.org/10.1109/TCSI.2016.2620520},
doi = {10.1109/TCSI.2016.2620520},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/YangTLJCC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/LiGMTASGCLDN17,
author = {Xueqing Li and
Sumitha George and
Kaisheng Ma and
Wei{-}Yu Tsai and
Ahmedullah Aziz and
John Sampson and
Sumeet Kumar Gupta and
Meng{-}Fan Chang and
Yongpan Liu and
Suman Datta and
Vijaykrishnan Narayanan},
title = {Advancing Nonvolatile Computing With Nonvolatile {NCFET} Latches and
Flip-Flops},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {64-I},
number = {11},
pages = {2907--2919},
year = {2017},
url = {https://doi.org/10.1109/TCSI.2017.2702741},
doi = {10.1109/TCSI.2017.2702741},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/LiGMTASGCLDN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChakrabartyABBC17,
author = {Krishnendu Chakrabarty and
Massimo Alioto and
Bevan M. Baas and
Chirn Chye Boon and
Meng{-}Fan Chang and
Naehyuck Chang and
Yao{-}Wen Chang and
Chip{-}Hong Chang and
Shih{-}Chieh Chang and
Poki Chen and
Masud H. Chowdhury and
Pasquale Corsonello and
Ibrahim Abe M. Elfadel and
Said Hamdioui and
Masanori Hashimoto and
Tsung{-}Yi Ho and
Houman Homayoun and
Yuh{-}Shyan Hwang and
Rajiv V. Joshi and
Tanay Karnik and
Mehran Mozaffari Kermani and
Chulwoo Kim and
Tae{-}Hyoung Kim and
Jaydeep P. Kulkarni and
Eren Kursun and
Erik Larsson and
Hai (Helen) Li and
Huawei Li and
Patrick P. Mercier and
Prabhat Mishra and
Makoto Nagata and
Arun S. Natarajan and
Koji Nii and
Partha Pratim Pande and
Ioannis Savidis and
Mingoo Seok and
Sheldon X.{-}D. Tan and
Mark M. Tehranipoor and
Aida Todri{-}Sanial and
Miroslav N. Velev and
Xiaoqing Wen and
Jiang Xu and
Wei Zhang and
Zhengya Zhang and
Stacey Weber Jackson},
title = {Editorial},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {1},
pages = {1--20},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2638578},
doi = {10.1109/TVLSI.2016.2638578},
timestamp = {Fri, 02 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChakrabartyABBC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TsaiYPLTCC17,
author = {Hsiang{-}Jen Tsai and
Keng{-}Hao Yang and
Yin{-}Chi Peng and
Chien{-}Chen Lin and
Ya{-}Han Tsao and
Meng{-}Fan Chang and
Tien{-}Fu Chen},
title = {Energy-Efficient {TCAM} Search Engine Design Using Priority-Decision
in Memory Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {3},
pages = {962--973},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2624990},
doi = {10.1109/TVLSI.2016.2624990},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TsaiYPLTCC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SunLCCCCY17,
author = {Xiaoyu Sun and
Rui Liu and
Yi{-}Ju Chen and
Hsiao{-}Yun Chiu and
Wei{-}Hao Chen and
Meng{-}Fan Chang and
Shimeng Yu},
title = {Low-VDD Operation of {SRAM} Synaptic Array for Implementing Ternary
Neural Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {10},
pages = {2962--2965},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2727528},
doi = {10.1109/TVLSI.2017.2727528},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SunLCCCCY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TsaiCPTCZCC17,
author = {Hsiang{-}Jen Tsai and
Chien{-}Chih Chen and
Yin{-}Chi Peng and
Ya{-}Han Tsao and
Yen{-}Ning Chiang and
Wei{-}Cheng Zhao and
Meng{-}Fan Chang and
Tien{-}Fu Chen},
title = {A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous
Discrete Finite Automata},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {12},
pages = {3302--3316},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2671408},
doi = {10.1109/TVLSI.2017.2671408},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TsaiCPTCZCC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/DouCCLLHC17,
author = {Chunmeng Dou and
Wei{-}Hao Chen and
Yi{-}Ju Chen and
Huan{-}Ting Lin and
Wei{-}Yu Lin and
Mon{-}Shu Ho and
Meng{-}Fan Chang},
editor = {Yajie Qin and
Zhiliang Hong and
Ting{-}Ao Tang},
title = {Challenges of emerging memory and memristor based circuits: Nonvolatile
logics, IoT security, deep learning and neuromorphic computing},
booktitle = {12th {IEEE} International Conference on ASIC, {ASICON} 2017, Guiyang,
China, October 25-28, 2017},
pages = {140--143},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASICON.2017.8252431},
doi = {10.1109/ASICON.2017.8252431},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/asicon/DouCCLLHC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/ZhangFDLFLHDCBL17,
author = {Feng Zhang and
Dongyu Fan and
Yuan Duan and
Jin Li and
Cong Fang and
Yun Li and
Xiaowei Han and
Lan Dai and
Cheng{-}Ying Chen and
Jinshun Bi and
Ming Liu and
Meng{-}Fan Chang},
title = {A 130nm 1Mb HfOx embedded {RRAM} macro using self-adaptive peripheral
circuit system techniques for 1.6X work temperature range},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2017, Seoul,
Korea (South), November 6-8, 2017},
pages = {173--176},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASSCC.2017.8240244},
doi = {10.1109/ASSCC.2017.8240244},
timestamp = {Mon, 06 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asscc/ZhangFDLFLHDCBL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ChenKLLLL0WYC17,
author = {Wei{-}Hao Chen and
Win{-}San Khwa and
Jun{-}Yi Li and
Wei{-}Yu Lin and
Huan{-}Ting Lin and
Yongpan Liu and
Yu Wang and
Huaqiang Wu and
Huazhong Yang and
Meng{-}Fan Chang},
title = {Circuit design for beyond von Neumann applications using emerging
memory: From nonvolatile logics to neuromorphic computing},
booktitle = {18th International Symposium on Quality Electronic Design, {ISQED}
2017, Santa Clara, CA, USA, March 14-15, 2017},
pages = {23--28},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISQED.2017.7918287},
doi = {10.1109/ISQED.2017.7918287},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/ChenKLLLL0WYC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangDDMSV17,
author = {Meng{-}Fan Chang and
Jun Deguchi and
Vivek De and
Masato Motomura and
Shinichiro Shiratake and
Marian Verhelst},
title = {{F3:} Beyond the horizon of conventional computing: From deep learning
to neuromorphic systems},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {506--508},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870481},
doi = {10.1109/ISSCC.2017.7870481},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChangDDMSV17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SrinivasaMCHLCG17,
author = {Srivatsa Rangachar Srinivasa and
Karthik Mohan and
Wei{-}Hao Chen and
Kuo{-}Hsinag Hsu and
Xueqing Li and
Meng{-}Fan Chang and
Sumeet Kumar Gupta and
John Sampson and
Vijaykrishnan Narayanan},
title = {Improving {FPGA} Design with Monolithic 3D Integration Using High
Dense Inter-Stack Via},
booktitle = {2017 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2017,
Bochum, Germany, July 3-5, 2017},
pages = {128--133},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ISVLSI.2017.31},
doi = {10.1109/ISVLSI.2017.31},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/SrinivasaMCHLCG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangHLCKCYTCS16,
author = {Meng{-}Fan Chang and
Li{-}Yue Huang and
Wen{-}Zhang Lin and
Yen{-}Ning Chiang and
Chia{-}Chen Kuo and
Ching{-}Hao Chuang and
Keng{-}Hao Yang and
Hsiang{-}Jen Tsai and
Tien{-}Fu Chen and
Shyh{-}Shyuan Sheu},
title = {A ReRAM-Based 4T2R Nonvolatile {TCAM} Using RC-Filtered Stress-Decoupled
Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and
Big-Data Processing},
journal = {{IEEE} J. Solid State Circuits},
volume = {51},
number = {11},
pages = {2786--2798},
year = {2016},
url = {https://doi.org/10.1109/JSSC.2016.2602218},
doi = {10.1109/JSSC.2016.2602218},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChangHLCKCYTCS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/biocas/ChouCCCTSHCYCT16,
author = {Ting{-}I Chou and
Shih{-}Wen Chiu and
Kwuang{-}Han Chang and
Yi{-}Ju Chen and
Chen{-}Ting Tang and
Chung{-}Hung Shih and
Chih{-}Cheng Hsieh and
Meng{-}Fan Chang and
Chia{-}Hsiang Yang and
Herming Chiueh and
Kea{-}Tiong Tang},
title = {Design of a 0.5 {V} 1.68mW nose-on-a-chip for rapid screen of chronic
obstructive pulmonary disease},
booktitle = {{IEEE} Biomedical Circuits and Systems Conference, BioCAS 2016, Shanghai,
China, October 17-19, 2016},
pages = {592--595},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/BioCAS.2016.7833864},
doi = {10.1109/BIOCAS.2016.7833864},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/biocas/ChouCCCTSHCYCT16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/GeorgeMALKSCDSG16,
author = {Sumitha George and
Kaisheng Ma and
Ahmedullah Aziz and
Xueqing Li and
Asif Islam Khan and
Sayeef S. Salahuddin and
Meng{-}Fan Chang and
Suman Datta and
John Sampson and
Sumeet Kumar Gupta and
Vijaykrishnan Narayanan},
title = {Nonvolatile memory design based on ferroelectric FETs},
booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
2016, Austin, TX, USA, June 5-9, 2016},
pages = {118:1--118:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2897937.2898050},
doi = {10.1145/2897937.2898050},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/GeorgeMALKSCDSG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChangCCSKCSI16,
author = {Meng{-}Fan Chang and
Ching{-}Hao Chuang and
Yen{-}Ning Chiang and
Shyh{-}Shyuan Sheu and
Chia{-}Chen Kuo and
Hsiang{-}Yun Cheng and
John Sampson and
Mary Jane Irwin},
title = {Designs of emerging memory based non-volatile {TCAM} for Internet-of-Things
(IoT) and big-data processing: {A} 5T2R universal cell},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016,
Montr{\'{e}}al, QC, Canada, May 22-25, 2016},
pages = {1142--1145},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISCAS.2016.7527447},
doi = {10.1109/ISCAS.2016.7527447},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChangCCSKCSI16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LiuWLSLYLWWKLKW16,
author = {Yongpan Liu and
Zhibo Wang and
Albert Lee and
Fang Su and
Chieh{-}Pu Lo and
Zhe Yuan and
Chien{-}Chen Lin and
Qi Wei and
Yu Wang and
Ya{-}Chin King and
Chrong Jung Lin and
Pedram Khalili and
Kang{-}Lung Wang and
Meng{-}Fan Chang and
Huazhong Yang},
title = {4.7 {A} 65nm ReRAM-enabled nonvolatile processor with 6{\texttimes}
reduction in restore time and 4{\texttimes} higher clock frequency
using adaptive data retention and self-write-termination nonvolatile
logic},
booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2016, San Francisco, CA, USA, January 31 - February 4, 2016},
pages = {84--86},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISSCC.2016.7417918},
doi = {10.1109/ISSCC.2016.7417918},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/LiuWLSLYLWWKLKW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KhwaCWLSYCWLBKL16,
author = {Win{-}San Khwa and
Meng{-}Fan Chang and
Jau{-}Yi Wu and
Ming{-}Hsiu Lee and
Tzu{-}Hsiang Su and
Keng{-}Hao Yang and
Tien{-}Fu Chen and
Tien{-}Yen Wang and
Hsiang{-}Pang Li and
Matthew BrightSky and
SangBum Kim and
Hsiang{-}Lam Lung and
Chung Lam},
title = {7.3 {A} resistance-drift compensation scheme to reduce {MLC} {PCM}
raw {BER} by over 100{\texttimes} for storage-class memory applications},
booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2016, San Francisco, CA, USA, January 31 - February 4, 2016},
pages = {134--135},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISSCC.2016.7417943},
doi = {10.1109/ISSCC.2016.7417943},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KhwaCWLSYCWLBKL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LinHLLCTYKLCC16,
author = {Chien{-}Chen Lin and
Jui{-}Yu Hung and
Wen{-}Zhang Lin and
Chieh{-}Pu Lo and
Yen{-}Ning Chiang and
Hsiang{-}Jen Tsai and
Geng{-}Hau Yang and
Ya{-}Chin King and
Chrong Jung Lin and
Tien{-}Fu Chen and
Meng{-}Fan Chang},
title = {7.4 {A} 256b-wordlength ReRAM-based {TCAM} with 1ns search-time and
14{\texttimes} improvement in wordlength-energyefficiency-density
product using 2.5T1R cell},
booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2016, San Francisco, CA, USA, January 31 - February 4, 2016},
pages = {136--137},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISSCC.2016.7417944},
doi = {10.1109/ISSCC.2016.7417944},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/LinHLLCTYKLCC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SuWLCL16,
author = {Fang Su and
Zhibo Wang and
Jinyang Li and
Meng{-}Fan Chang and
Yongpan Liu},
title = {Design of nonvolatile processors and applications},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753543},
doi = {10.1109/VLSI-SOC.2016.7753543},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SuWLCL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/ChangLCLKSK15,
author = {Meng{-}Fan Chang and
Albert Lee and
Pin{-}Cheng Chen and
Chrong Jung Lin and
Ya{-}Chin King and
Shyh{-}Shyuan Sheu and
Tzu{-}Kun Ku},
title = {Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile
Memory Using Memristive Devices},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {5},
number = {2},
pages = {183--193},
year = {2015},
url = {https://doi.org/10.1109/JETCAS.2015.2426531},
doi = {10.1109/JETCAS.2015.2426531},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esticas/ChangLCLKSK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HungCYKLSHHLSHC15,
author = {Chun{-}Hsiung Hung and
Meng{-}Fan Chang and
Yih{-}Shan Yang and
Yao{-}Jen Kuo and
Tzu{-}Neng Lai and
Shin{-}Jang Shen and
Jo{-}Yu Hsu and
Shuo{-}Nan Hung and
Hang{-}Ting Lue and
Yen{-}Hao Shih and
Shih{-}Lin Huang and
Ti{-}Wen Chen and
Tzung Shen Chen and
Chung Kuang Chen and
Chi{-}Yu Hung and
Chih{-}Yuan Lu},
title = {Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate
{BE-SONOS} {NAND} Flash Against Cross-Layer Process Variations},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {6},
pages = {1491--1501},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2015.2413841},
doi = {10.1109/JSSC.2015.2413841},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/HungCYKLSHHLSHC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangLLWSTC15,
author = {Meng{-}Fan Chang and
Yu{-}Fan Lin and
Yen{-}Chen Liu and
Jui{-}Jen Wu and
Shin{-}Jang Shen and
Wu{-}Chin Tsai and
Yu{-}Der Chih},
title = {An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read
Embedded Flash Macros},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {9},
pages = {2188--2198},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2015.2424972},
doi = {10.1109/JSSC.2015.2424972},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChangLLWSTC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangWCLYSKLLCC15,
author = {Meng{-}Fan Chang and
Jui{-}Jen Wu and
Tun{-}Fei Chien and
Yen{-}Chen Liu and
Ting{-}Chin Yang and
Wen{-}Chao Shen and
Ya{-}Chin King and
Chrong Jung Lin and
Ku{-}Feng Lin and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang},
title = {Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient
Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against
Resistance and Switch-Time Variations},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {11},
pages = {2786--2795},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2015.2472601},
doi = {10.1109/JSSC.2015.2472601},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChangWCLYSKLLCC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ChangYKYYCHSTCCKTK15,
author = {Meng{-}Fan Chang and
Shu{-}Meng Yang and
Chia{-}Chen Kuo and
Ting{-}Chin Yang and
Che{-}Ju Yeh and
Tun{-}Fei Chien and
Li{-}Yue Huang and
Shyh{-}Shyuan Sheu and
Pei{-}Ling Tseng and
Yu{-}Sheng Chen and
Frederick T. Chen and
Tzu{-}Kun Ku and
Ming{-}Jinn Tsai and
Ming{-}Jer Kao},
title = {Set-Triggered-Parallel-Reset Memristor Logic for High-Density Heterogeneous-Integration
Friendly Normally Off Applications},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {62-II},
number = {1},
pages = {80--84},
year = {2015},
url = {https://doi.org/10.1109/TCSII.2014.2362713},
doi = {10.1109/TCSII.2014.2362713},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ChangYKYYCHSTCCKTK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChangLLHCKCTKCL15,
author = {Meng{-}Fan Chang and
Albert Lee and
Chien{-}Chen Lin and
Mon{-}Shu Ho and
Ping{-}Cheng Chen and
Chia{-}Chen Kuo and
Ming{-}Pin Chen and
Pei{-}Ling Tseng and
Tzu{-}Kun Ku and
Chien{-}Fu Chen and
Kai{-}Shin Li and
Jia{-}Min Shieh},
title = {Read circuits for resistive memory (ReRAM) and memristor-based nonvolatile
Logics},
booktitle = {The 20th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2015, Chiba, Japan, January 19-22, 2015},
pages = {569--574},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASPDAC.2015.7059068},
doi = {10.1109/ASPDAC.2015.7059068},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ChangLLHCKCTKCL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/TsaiYPLTCC15,
author = {Hsiang{-}Jen Tsai and
Keng{-}Hao Yang and
Yin{-}Chi Peng and
Chien{-}Chen Lin and
Ya{-}Han Tsao and
Meng{-}Fan Chang and
Tien{-}Fu Chen},
title = {Energy-efficient non-volatile {TCAM} search engine design using priority-decision
in memory technology for {DPI}},
booktitle = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco,
CA, USA, June 7-11, 2015},
pages = {100:1--100:6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2744769.2744836},
doi = {10.1145/2744769.2744836},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/TsaiYPLTCC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiuLLWLMLCJ0SY15,
author = {Yongpan Liu and
Zewei Li and
Hehe Li and
Yiqun Wang and
Xueqing Li and
Kaisheng Ma and
Shuangchen Li and
Meng{-}Fan Chang and
John Sampson and
Yuan Xie and
Jiwu Shu and
Huazhong Yang},
title = {Ambient energy harvesting nonvolatile processors: from circuit to
system},
booktitle = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco,
CA, USA, June 7-11, 2015},
pages = {150:1--150:6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2744769.2747910},
doi = {10.1145/2744769.2747910},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/LiuLLWLMLCJ0SY15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LiLZGSSZCLY15,
author = {Hehe Li and
Yongpan Liu and
Qinghang Zhao and
Yizi Gu and
Xiao Sheng and
Guangyu Sun and
Chao Zhang and
Meng{-}Fan Chang and
Rong Luo and
Huazhong Yang},
editor = {Wolfgang Nebel and
David Atienza},
title = {An energy efficient backup scheme with low inrush current for nonvolatile
{SRAM} in energy harvesting sensor nodes},
booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe
Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March
9-13, 2015},
pages = {7--12},
publisher = {{ACM}},
year = {2015},
url = {http://dl.acm.org/citation.cfm?id=2755756},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/LiLZGSSZCLY15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangCCSWY15,
author = {Meng{-}Fan Chang and
Chien{-}Fu Chen and
Ting{-}Hao Chang and
Chi{-}Chang Shuai and
Yen{-}Yao Wang and
Hiroyuki Yamauchi},
title = {17.3 {A} 28nm 256kb 6T-SRAM with 280mV improvement in {VMIN} using
a dual-split-control assist scheme},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7063052},
doi = {10.1109/ISSCC.2015.7063052},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChangCCSWY15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangLLKYTCSTLK15,
author = {Meng{-}Fan Chang and
Chien{-}Chen Lin and
Albert Lee and
Chia{-}Chen Kuo and
Geng{-}Hau Yang and
Hsiang{-}Jen Tsai and
Tien{-}Fu Chen and
Shyh{-}Shyuan Sheu and
Pei{-}Ling Tseng and
Heng{-}Yuan Lee and
Tzu{-}Kun Ku},
title = {17.5 {A} 3T1R nonvolatile {TCAM} using {MLC} ReRAM with Sub-1ns search
time},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7063054},
doi = {10.1109/ISSCC.2015.7063054},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChangLLKYTCSTLK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/LeeLYC15,
author = {Albert Lee and
Chien{-}Chen Lin and
Ting{-}Chin Yang and
Meng{-}Fan Chang},
title = {An embedded ReRAM using a small-offset sense amplifier for low-voltage
operations},
booktitle = {{VLSI} Design, Automation and Test, {VLSI-DAT} 2015, Hsinchu, Taiwan,
April 27-29, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-DAT.2015.7114532},
doi = {10.1109/VLSI-DAT.2015.7114532},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/LeeLYC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LeeCLCHKTSK15,
author = {Albert Lee and
Meng{-}Fan Chang and
Chien{-}Chen Lin and
Chien{-}Fu Chen and
Mon{-}Shu Ho and
Chia{-}Chen Kuo and
Pei{-}Ling Tseng and
Shyh{-}Shyuan Sheu and
Tzu{-}Kun Ku},
title = {RRAM-based 7T1R nonvolatile {SRAM} with 2x reduction in store energy
and 94x reduction in restore energy for frequent-off instant-on applications},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2015, Kyoto, Japan, June 17-19,
2015},
pages = {76},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSIC.2015.7231368},
doi = {10.1109/VLSIC.2015.7231368},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LeeCLCHKTSK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangKSLKCKTWC14,
author = {Meng{-}Fan Chang and
Chia{-}Chen Kuo and
Shyh{-}Shyuan Sheu and
Chorng{-}Jung Lin and
Ya{-}Chin King and
Frederick T. Chen and
Tzu{-}Kun Ku and
Ming{-}Jinn Tsai and
Jui{-}Jen Wu and
Yu{-}Der Chih},
title = {Area-Efficient Embedded Resistive {RAM} (ReRAM) Macros Using Logic-Process
Vertical-Parasitic-BJT {(VPBJT)} Switches and Read-Disturb-Free Temperature-Aware
Current-Mode Read Scheme},
journal = {{IEEE} J. Solid State Circuits},
volume = {49},
number = {4},
pages = {908--916},
year = {2014},
url = {https://doi.org/10.1109/JSSC.2013.2297417},
doi = {10.1109/JSSC.2013.2297417},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChangKSLKCKTWC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tbcas/ChiuWCCWCTCSKWCHCLCYCST14,
author = {Shih{-}Wen Chiu and
Jen{-}Huo Wang and
Kwuang{-}Han Chang and
Ting{-}Hau Chang and
Chia{-}Min Wang and
Chia{-}Lin Chang and
Chen{-}Ting Tang and
Chien{-}Fu Chen and
Chung{-}Hung Shih and
Han{-}Wen Kuo and
Li{-}Chun Wang and
Hsin Chen and
Chih{-}Cheng Hsieh and
Meng{-}Fan Chang and
Yi{-}Wen Liu and
Tsan{-}Jieh Chen and
Chia{-}Hsiang Yang and
Herming Chiueh and
Jyuo{-}Min Shyu and
Kea{-}Tiong Tang},
title = {A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated
Pneumonia},
journal = {{IEEE} Trans. Biomed. Circuits Syst.},
volume = {8},
number = {6},
pages = {765--778},
year = {2014},
url = {https://doi.org/10.1109/TBCAS.2014.2377754},
doi = {10.1109/TBCAS.2014.2377754},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tbcas/ChiuWCCWCTCSKWCHCLCYCST14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/ChangWHKLHKS14,
author = {Meng{-}Fan Chang and
Che{-}Wei Wu and
Jui{-}Yu Hung and
Ya{-}Chin King and
Chomg{-}Jung Lin and
Mon{-}Shu Ho and
Chia{-}Cheng Kuo and
Shyh{-}Shyuan Sheu},
title = {A low-power subthreshold-to-superthreshold level-shifter for sub-0.5V
embedded resistive {RAM} (ReRAM) macro in ultra low-voltage chips},
booktitle = {2014 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
2014, Ishigaki, Japan, November 17-20, 2014},
pages = {695--698},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/APCCAS.2014.7032876},
doi = {10.1109/APCCAS.2014.7032876},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/apccas/ChangWHKLHKS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/LinSKTCSLTLLCLH14,
author = {Wen{-}Pin Lin and
Shyh{-}Shyuan Sheu and
Chia{-}Chen Kuo and
Pei{-}Ling Tseng and
Meng{-}Fan Chang and
Keng{-}Li Su and
Chih{-}Sheng Lin and
Kan{-}Hsueh Tsai and
Sih{-}Han Lee and
Szu{-}Chieh Liu and
Yu{-}Sheng Chen and
Heng{-}Yuan Lee and
Ching{-}Chih Hsu and
Frederick T. Chen and
Tzu{-}Kun Ku and
Ming{-}Jinn Tsai and
Ming{-}Jer Kao},
title = {A nonvolatile look-up table using ReRAM for reconfigurable logic},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2014, KaoHsiung,
Taiwan, November 10-12, 2014},
pages = {133--136},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASSCC.2014.7008878},
doi = {10.1109/ASSCC.2014.7008878},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/asscc/LinSKTCSLTLLCLH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/TsaiCYYHCCC14,
author = {Hsiang{-}Jen Tsai and
Chien{-}Chih Chen and
Keng{-}Hao Yang and
Ting{-}Chin Yang and
Li{-}Yue Huang and
Ching{-}Hao Chuang and
Meng{-}Fan Chang and
Tien{-}Fu Chen},
title = {Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile
{SRAM} Caches using Redundant Store Elimination},
booktitle = {The 51st Annual Design Automation Conference 2014, {DAC} '14, San
Francisco, CA, USA, June 1-5, 2014},
pages = {38:1--38:6},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2593069.2593153},
doi = {10.1145/2593069.2593153},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/TsaiCYYHCCC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangWCLYSKLLCN14,
author = {Meng{-}Fan Chang and
Jui{-}Jen Wu and
Tun{-}Fei Chien and
Yen{-}Chen Liu and
Ting{-}Chin Yang and
Wen{-}Chao Shen and
Ya{-}Chin King and
Chorng{-}Jung Lin and
Ku{-}Feng Lin and
Yu{-}Der Chih and
Sreedhar Natarajan and
Tsung{-}Yung Jonathan Chang},
title = {19.4 embedded 1Mb ReRAM in 28nm {CMOS} with 0.27-to-1V read using
swing-sample-and-couple sense amplifier and self-boost-write-termination
scheme},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {332--333},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757457},
doi = {10.1109/ISSCC.2014.6757457},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChangWCLYSKLLCN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/TangCSCYYWHCCHC14,
author = {Kea{-}Tiong Tang and
Shih{-}Wen Chiu and
Chung{-}Hung Shih and
Chia{-}Ling Chang and
Chia{-}Min Yang and
Da{-}Jeng Yao and
Jen{-}Huo Wang and
Chien{-}Ming Huang and
Hsin Chen and
Kwuang{-}Han Chang and
Chih{-}Cheng Hsieh and
Ting{-}Hau Chang and
Meng{-}Fan Chang and
Chia{-}Min Wang and
Yi{-}Wen Liu and
Tsan{-}Jieh Chen and
Chia{-}Hsiang Yang and
Herming Chiueh and
Jyuo{-}Min Shyu},
title = {24.5 {A} 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated
pneumonia},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {420--421},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757496},
doi = {10.1109/ISSCC.2014.6757496},
timestamp = {Mon, 04 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/TangCSCYYWHCCHC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/newcas/ChiuWCWCHCWT14,
author = {Shih{-}Wen Chiu and
Jen{-}Huo Wang and
Kwuang{-}Han Chang and
Hsiang{-}Chiu Wu and
Hsin Chen and
Chih{-}Cheng Hsieh and
Meng{-}Fan Chang and
Guoxing Wang and
Kea{-}Tiong Tang},
title = {A signal acquisition and processing chip with built-in cluster for
chemiresistive gas sensor array},
booktitle = {{IEEE} 12th International New Circuits and Systems Conference, {NEWCAS}
2014, Trois-Rivieres, QC, Canada, June 22-25, 2014},
pages = {428--431},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/NEWCAS.2014.6934074},
doi = {10.1109/NEWCAS.2014.6934074},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/newcas/ChiuWCWCHCWT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/HuangCCKCYTCSSC14,
author = {Li{-}Yue Huang and
Meng{-}Fan Chang and
Ching{-}Hao Chuang and
Chia{-}Chen Kuo and
Chien{-}Fu Chen and
Geng{-}Hau Yang and
Hsiang{-}Jen Tsai and
Tien{-}Fu Chen and
Shyh{-}Shyuan Sheu and
Keng{-}Li Su and
Frederick T. Chen and
Tzu{-}Kun Ku and
Ming{-}Jinn Tsai and
Ming{-}Jer Kao},
title = {ReRAM-based 4T2R nonvolatile {TCAM} with 7x NVM-stress reduction,
and 4x improvement in speed-wordlength-capacity for normally-off instant-on
filter-based search engines used in big-data processing},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2014, Digest of Technical Papers,
Honolulu, HI, USA, June 10-13, 2014},
pages = {1--2},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSIC.2014.6858404},
doi = {10.1109/VLSIC.2014.6858404},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/HuangCCKCYTCSSC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/ChenLLCCC13,
author = {Wen{-}Tsuen Chen and
Youn{-}Long Lin and
Chen{-}Yi Lee and
Jeng{-}Long Chiang and
Meng{-}Fan Chang and
Shih{-}Chieh Chang},
title = {Strengthening Modern Electronics Industry Through the National Program
for Intelligent Electronics in Taiwan},
journal = {{IEEE} Access},
volume = {1},
pages = {123--130},
year = {2013},
url = {https://doi.org/10.1109/ACCESS.2013.2260591},
doi = {10.1109/ACCESS.2013.2260591},
timestamp = {Wed, 04 Jul 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/ChenLLCCC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/YangCCCY13,
author = {Shu{-}Meng Yang and
Meng{-}Fan Chang and
Chi{-}Chuang Chiang and
Ming{-}Bin Chen and
Hiroyuki Yamauchi},
title = {Low-Voltage Embedded {NAND-ROM} Macros Using Data-Aware Sensing Reference
Scheme for VDDmin, Speed and Power Improvement},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {2},
pages = {611--623},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2012.2229068},
doi = {10.1109/JSSC.2012.2229068},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/YangCCCY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangSLWLKLLCY13,
author = {Meng{-}Fan Chang and
Shin{-}Jang Shen and
Chia{-}Chi Liu and
Che{-}Wei Wu and
Yu{-}Fan Lin and
Ya{-}Chin King and
Chorng{-}Jung Lin and
Hung{-}Jen Liao and
Yu{-}Der Chih and
Hiroyuki Yamauchi},
title = {An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier
for Small-Cell-Current Nonvolatile Memory},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {3},
pages = {864--877},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2012.2235013},
doi = {10.1109/JSSC.2012.2235013},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChangSLWLKLLCY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangSLWKCYCLLCSKKT13,
author = {Meng{-}Fan Chang and
Shyh{-}Shyuan Sheu and
Ku{-}Feng Lin and
Che{-}Wei Wu and
Chia{-}Chen Kuo and
Pi{-}Feng Chiu and
Yih{-}Shan Yang and
Yu{-}Sheng Chen and
Heng{-}Yuan Lee and
Chen{-}Hsin Lien and
Frederick T. Chen and
Keng{-}Li Su and
Tzu{-}Kun Ku and
Ming{-}Jer Kao and
Ming{-}Jinn Tsai},
title = {A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive
{RAM} (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode
Read Schemes},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {3},
pages = {878--891},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2012.2230515},
doi = {10.1109/JSSC.2012.2230515},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChangSLWKCYCLLCSKKT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangWKSYLSKLC13,
author = {Meng{-}Fan Chang and
Che{-}Wei Wu and
Chia{-}Chen Kuo and
Shin{-}Jang Shen and
Sue{-}Meng Yang and
Ku{-}Feng Lin and
Wen{-}Chao Shen and
Ya{-}Chin King and
Chorng{-}Jung Lin and
Yu{-}Der Chih},
title = {A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 {V} 4 Mb 65
nm Logic-Process Compatible Embedded Resistive {RAM} (ReRAM) Macro},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {9},
pages = {2250--2259},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2013.2259713},
doi = {10.1109/JSSC.2013.2259713},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChangWKSYLSKLC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangCCYKWSCWYY13,
author = {Meng{-}Fan Chang and
Ming{-}Bin Chen and
Lai{-}Fu Chen and
Shu{-}Meng Yang and
Yao{-}Jen Kuo and
Jui{-}Jen Wu and
Hsiu{-}Yun Su and
Yuan{-}Hua Chu and
Wen{-}Chin Wu and
Tzu{-}Yi Yang and
Hiroyuki Yamauchi},
title = {A Sub-0.3 {V} Area-Efficient L-Shaped 7T {SRAM} With Read Bitline
Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V\({}_{\mbox{TH}}\)
Read-Port, and Offset Cell {VDD} Biasing Techniques},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {10},
pages = {2558--2569},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2013.2273835},
doi = {10.1109/JSSC.2013.2273835},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChangCCYKWSCWYY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/LiWWACK13,
author = {Jin{-}Fu Li and
Cheng{-}Wen Wu and
Masahiro Aoyagi and
Meng{-}Fan Marvin Chang and
Ding{-}Ming Kwai},
title = {Special session 4C: Hot topic 3D-IC design and test},
booktitle = {31st {IEEE} {VLSI} Test Symposium, {VTS} 2013, Berkeley, CA, USA,
April 29 - May 2, 2013},
pages = {1},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/VTS.2013.6548900},
doi = {10.1109/VTS.2013.6548900},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vts/LiWWACK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChenCLCSLWCY12,
author = {Yen{-}Huei Chen and
Shao{-}Yu Chou and
Quincy Li and
Wei{-}Min Chan and
Dar Sun and
Hung{-}Jen Liao and
Ping Wang and
Meng{-}Fan Chang and
Hiroyuki Yamauchi},
title = {Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset
Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance
Margin in a 40 nm Fully Functional Embedded {SRAM}},
journal = {{IEEE} J. Solid State Circuits},
volume = {47},
number = {4},
pages = {969--980},
year = {2012},
url = {https://doi.org/10.1109/JSSC.2012.2185180},
doi = {10.1109/JSSC.2012.2185180},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChenCLCSLWCY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChiuCWCSCT12,
author = {Pi{-}Feng Chiu and
Meng{-}Fan Chang and
Che{-}Wei Wu and
Ching{-}Hao Chuang and
Shyh{-}Shyuan Sheu and
Yu{-}Sheng Chen and
Ming{-}Jinn Tsai},
title = {Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and {SRAM} With
Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power
Mobile Applications},
journal = {{IEEE} J. Solid State Circuits},
volume = {47},
number = {6},
pages = {1483--1496},
year = {2012},
url = {https://doi.org/10.1109/JSSC.2012.2192661},
doi = {10.1109/JSSC.2012.2192661},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChiuCWCSCT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/WuCLLL12,
author = {Jui{-}Jen Wu and
Meng{-}Fan Chang and
Shau{-}Wei Lu and
Robert Lo and
Quincy Li},
title = {A 45-nm Dual-Port {SRAM} Utilizing Write-Assist Cells Against Simultaneous
Access Disturbances},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {59-II},
number = {11},
pages = {790--794},
year = {2012},
url = {https://doi.org/10.1109/TCSII.2012.2228398},
doi = {10.1109/TCSII.2012.2228398},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/WuCLLL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChangCCCYCS12,
author = {Meng{-}Fan Chang and
Ching{-}Hao Chuang and
Min{-}Ping Chen and
Lai{-}Fu Chen and
Hiroyuki Yamauchi and
Pi{-}Feng Chiu and
Shyh{-}Shyuan Sheu},
title = {Endurance-aware circuit designs of nonvolatile logic and nonvolatile
sram using resistive memory (memristor) device},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {329--334},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6164968},
doi = {10.1109/ASPDAC.2012.6164968},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ChangCCCYCS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangWKSLYKLC12,
author = {Meng{-}Fan Chang and
Che{-}Wei Wu and
Chia{-}Chen Kuo and
Shin{-}Jang Shen and
Ku{-}Feng Lin and
Shu{-}Meng Yang and
Ya{-}Chin King and
Chorng{-}Jung Lin and
Yu{-}Der Chih},
title = {A 0.5V 4Mb logic-process compatible embedded resistive {RAM} (ReRAM)
in 65nm {CMOS} using low-voltage current-mode sensing scheme with
45ns random read time},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {434--436},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6177079},
doi = {10.1109/ISSCC.2012.6177079},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChangWKSLYKLC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChenCCYKWHSCWYY12,
author = {Ming{-}Pin Chen and
Lai{-}Fu Chen and
Meng{-}Fan Chang and
Shu{-}Meng Yang and
Yao{-}Jen Kuo and
Jui{-}Jen Wu and
Mon{-}Shu Ho and
Hsiu{-}Yun Su and
Yuan{-}Hua Chu and
Wen{-}Chin Wu and
Tzu{-}Yi Yang and
Hiroyuki Yamauchi},
title = {A 260mV L-shaped 7T {SRAM} with bit-line {(BL)} Swing expansion schemes
based on boosted BL, asymmetric-VTH read-port, and offset cell {VDD}
biasing techniques},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
13-15, 2012},
pages = {112--113},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSIC.2012.6243815},
doi = {10.1109/VLSIC.2012.6243815},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ChenCCYKWHSCWYY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/SheuCCCLLCCCT11,
author = {Shyh{-}Shyuan Sheu and
Kuo{-}Hsing Cheng and
Meng{-}Fan Chang and
Pei{-}Chia Chiang and
Wen{-}Pin Lin and
Heng{-}Yuan Lee and
Pang{-}Shiu Chen and
Yu{-}Sheng Chen and
Frederick T. Chen and
Ming{-}Jinn Tsai},
title = {Fast-Write Resistive {RAM} {(RRAM)} for Embedded Applications},
journal = {{IEEE} Des. Test Comput.},
volume = {28},
number = {1},
pages = {64--71},
year = {2011},
url = {https://doi.org/10.1109/MDT.2010.96},
doi = {10.1109/MDT.2010.96},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/SheuCCCLLCCCT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangCCW11,
author = {Meng{-}Fan Chang and
Shi{-}Wei Chang and
Po{-}Wei Chou and
Wei{-}Cheng Wu},
title = {A 130 mV {SRAM} With Expanded Write and Read Margins for Subthreshold
Applications},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {2},
pages = {520--529},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2010.2091321},
doi = {10.1109/JSSC.2010.2091321},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChangCCW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WuCCCCLCCWY11,
author = {Jui{-}Jen Wu and
Yen{-}Hui Chen and
Meng{-}Fan Chang and
Po{-}Wei Chou and
Chien{-}Yuan Chen and
Hung{-}Jen Liao and
Ming{-}Bin Chen and
Yuan{-}Hua Chu and
Wen{-}Chin Wu and
Hiroyuki Yamauchi},
title = {A Large Sigma {V} \({}_{\mbox{TH}}\) /VDD Tolerant Zigzag 8T {SRAM}
With Area-Efficient Decoupled Differential Sensing and Fast Write-Back
Scheme},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {4},
pages = {815--827},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2011.2109440},
doi = {10.1109/JSSC.2011.2109440},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/WuCCCCLCCWY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tbcas/TangCCHS11,
author = {Kea{-}Tiong Tang and
Shih{-}Wen Chiu and
Meng{-}Fan Chang and
Chih{-}Cheng Hsieh and
Jyuo{-}Min Shyu},
title = {A Low-Power Electronic Nose Signal-Processing Chip for a Portable
Artificial Olfaction System},
journal = {{IEEE} Trans. Biomed. Circuits Syst.},
volume = {5},
number = {4},
pages = {380--390},
year = {2011},
url = {https://doi.org/10.1109/TBCAS.2011.2116786},
doi = {10.1109/TBCAS.2011.2116786},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tbcas/TangCCHS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/ChangCWCS11,
author = {Meng{-}Fan Chang and
Pi{-}Feng Chiu and
Wei{-}Cheng Wu and
Ching{-}Hao Chuang and
Shyh{-}Shyuan Sheu},
title = {Challenges and trends in low-power 3D die-stacked {IC} designs using
RAM, memristor logic, and resistive memory (ReRAM)},
booktitle = {2011 {IEEE} 9th International Conference on ASIC, {ASICON} 2011, Xiamen,
China, October 25-28, 2011},
pages = {299--302},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASICON.2011.6157181},
doi = {10.1109/ASICON.2011.6157181},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/asicon/ChangCWCS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChangCS11,
author = {Meng{-}Fan Chang and
Pi{-}Feng Chiu and
Shyh{-}Shyuan Sheu},
title = {Circuit design challenges in embedded memory and resistive {RAM} {(RRAM)}
for mobile SoC and 3D-IC},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {197--203},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722184},
doi = {10.1109/ASPDAC.2011.5722184},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ChangCS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SheuCLWCCKYCLLLGWCSLCWKKT11,
author = {Shyh{-}Shyuan Sheu and
Meng{-}Fan Chang and
Ku{-}Feng Lin and
Che{-}Wei Wu and
Yu{-}Sheng Chen and
Pi{-}Feng Chiu and
Chia{-}Chen Kuo and
Yih{-}Shan Yang and
Pei{-}Chia Chiang and
Wen{-}Pin Lin and
Che{-}He Lin and
Heng{-}Yuan Lee and
Peiyi Gu and
Sumin Wang and
Frederick T. Chen and
Keng{-}Li Su and
Chen{-}Hsin Lien and
Kuo{-}Hsing Cheng and
Hsin{-}Tun Wu and
Tzu{-}Kun Ku and
Ming{-}Jer Kao and
Ming{-}Jinn Tsai},
title = {A 4Mb embedded {SLC} resistive-RAM macro with 7.2ns read-write random-access
time and 160ns MLC-access capability},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
2011},
pages = {200--202},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISSCC.2011.5746281},
doi = {10.1109/ISSCC.2011.5746281},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/SheuCLWCCKYCLLLGWCSLCWKKT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangSLWLWHLKLLCY11,
author = {Meng{-}Fan Chang and
Shin{-}Jang Shen and
Chia{-}Chi Liu and
Che{-}Wei Wu and
Yu{-}Fan Lin and
Shang{-}Chi Wu and
Chia{-}En Huang and
Han{-}Chao Lai and
Ya{-}Chin King and
Chorng{-}Jung Lin and
Hung{-}Jen Liao and
Yu{-}Der Chih and
Hiroyuki Yamauchi},
title = {An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current
nonvolatile memory},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
2011},
pages = {206--208},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISSCC.2011.5746284},
doi = {10.1109/ISSCC.2011.5746284},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChangSLWLWHLKLLCY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangWCCCLLY10,
author = {Meng{-}Fan Chang and
Jui{-}Jen Wu and
Kuang{-}Ting Chen and
Yung{-}Chi Chen and
Yen{-}Hui Chen and
Robin Lee and
Hung{-}Jen Liao and
Hiroyuki Yamauchi},
title = {A Differential Data-Aware Power-Supplied {(D} \({}^{\mbox{2}}\) {AP)}
8T {SRAM} Cell With Expanded Write/Read Stabilities for Lower VDDmin
Applications},
journal = {{IEEE} J. Solid State Circuits},
volume = {45},
number = {6},
pages = {1234--1245},
year = {2010},
url = {https://doi.org/10.1109/JSSC.2010.2048496},
doi = {10.1109/JSSC.2010.2048496},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChangWCCCLLY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangYLCCL10,
author = {Meng{-}Fan Chang and
Shu{-}Meng Yang and
Chih{-}Wei Liang and
Chih{-}Chyuang Chiang and
Pi{-}Feng Chiu and
Ku{-}Feng Lin},
title = {Noise-Immune Embedded {NAND-ROM} Using a Dynamic Split Source-Line
Scheme for VDDmin and Speed Improvements},
journal = {{IEEE} J. Solid State Circuits},
volume = {45},
number = {10},
pages = {2142--2155},
year = {2010},
url = {https://doi.org/10.1109/JSSC.2010.2060279},
doi = {10.1109/JSSC.2010.2060279},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChangYLCCL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ChangCC10,
author = {Meng{-}Fan Chang and
Yung{-}Chi Chen and
Chien{-}Fu Chen},
title = {A 0.45-V 300-MHz 10T Flowthrough {SRAM} With Expanded write/ read
Stability and Speed-Area-Wise Array for Sub-0.5-V Chips},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {57-II},
number = {12},
pages = {980--985},
year = {2010},
url = {https://doi.org/10.1109/TCSII.2010.2083130},
doi = {10.1109/TCSII.2010.2083130},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ChangCC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangYLCCLCWY10,
author = {Meng{-}Fan Chang and
Shu{-}Meng Yang and
Chih{-}Wei Liang and
Chih{-}Chyuang Chiang and
Pi{-}Feng Chiu and
Ku{-}Feng Lin and
Yuan{-}Hua Chu and
Wen{-}Chin Wu and
Hiroyuki Yamauchi},
title = {A 0.29V embedded {NAND-ROM} in 90nm {CMOS} for ultra-low-voltage applications},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {266--267},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5433914},
doi = {10.1109/ISSCC.2010.5433914},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChangYLCCLCWY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangS09,
author = {Meng{-}Fan Chang and
Shin{-}Jang Shen},
title = {A Process Variation Tolerant Embedded Split-Gate Flash Memory Using
Pre-Stable Current Sensing Scheme},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {3},
pages = {987--994},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2009.2013763},
doi = {10.1109/JSSC.2009.2013763},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChangS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ChangYC09,
author = {Meng{-}Fan Chang and
Su{-}Meng Yang and
Kuang{-}Ting Chen},
title = {Wide V\({}_{\mbox{DD}}\) Embedded Asynchronous {SRAM} With Dual-Mode
Self-Timed Technique for Dynamic Voltage Systems},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {56-I},
number = {8},
pages = {1657--1667},
year = {2009},
url = {https://doi.org/10.1109/TCSI.2008.2010101},
doi = {10.1109/TCSI.2008.2010101},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ChangYC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangY09,
author = {Meng{-}Fan Chang and
Shu{-}Meng Yang},
title = {Analysis and Reduction of Supply Noise Fluctuations Induced by Embedded
Via-Programming {ROM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {17},
number = {6},
pages = {758--769},
year = {2009},
url = {https://doi.org/10.1109/TVLSI.2008.2006794},
doi = {10.1109/TVLSI.2008.2006794},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangY09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangCW06,
author = {Meng{-}Fan Chang and
Lih{-}Yih Chiou and
Kuei{-}Ann Wen},
title = {A full code-patterns coverage high-speed embedded {ROM} using dynamic
virtual guardian technique},
journal = {{IEEE} J. Solid State Circuits},
volume = {41},
number = {2},
pages = {496--506},
year = {2006},
url = {https://doi.org/10.1109/JSSC.2005.862343},
doi = {10.1109/JSSC.2005.862343},
timestamp = {Fri, 15 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChangCW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ChangCW06,
author = {Meng{-}Fan Chang and
Lih{-}Yih Chiou and
Kuei{-}Ann Wen},
title = {Crosstalk-insensitive via-programming ROMs using content-aware design
framework},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {53-II},
number = {6},
pages = {443--447},
year = {2006},
url = {https://doi.org/10.1109/TCSII.2006.873640},
doi = {10.1109/TCSII.2006.873640},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ChangCW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/KwaiCCYCHLLSLH06,
author = {Ding{-}Ming Kwai and
Yung{-}Fa Chou and
Meng{-}Fan Chang and
Su{-}Meng Yang and
Ding{-}Sheng Chen and
Min{-}Chung Hsu and
Yu{-}Zhen Liao and
Shiao{-}Yi Lin and
Yu{-}Ling Sung and
Chia{-}Hsin Lee and
Hsin{-}Kun Hsu},
title = {FlexiVia {ROM} Compiler Programmable on Different Via Layers Based
on Top Metal Assignment},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
pages = {28--33},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.14},
doi = {10.1109/MTDT.2006.14},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/KwaiCCYCHLLSLH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/KwaiHKCHCSPLCC06,
author = {Ding{-}Ming Kwai and
Ching{-}Hua Hsiao and
Chung{-}Ping Kuo and
Chi{-}Hsien Chuang and
Min{-}Chung Hsu and
Yi{-}Chun Chen and
Yu{-}Ling Sung and
Hsien{-}Yu Pan and
Chia{-}Hsin Lee and
Meng{-}Fan Chang and
Yung{-}Fa Chou},
title = {{SRAM} Cell Current in Low Leakage Design},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
pages = {65--70},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.28},
doi = {10.1109/MTDT.2006.28},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/KwaiHKCHCSPLCC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/ChangW05,
author = {Meng{-}Fan Chang and
Kuei{-}Ann Wen},
title = {Power and Substrate Noise Tolerance of Configurable Embedded Memories
in SoC},
journal = {J. {VLSI} Signal Process.},
volume = {41},
number = {1},
pages = {81--91},
year = {2005},
url = {https://doi.org/10.1007/s11265-005-6252-4},
doi = {10.1007/S11265-005-6252-4},
timestamp = {Wed, 20 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsisp/ChangW05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/ChangWK05,
author = {Meng{-}Fan Chang and
Kuei{-}Ann Wen and
Ding{-}Ming Kwai},
title = {Via-programmable read-only memory design for full code coverage using
a dynamic bit-line shielding technique},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {16--21},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.36},
doi = {10.1109/MTDT.2005.36},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/ChangWK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ChangWK04,
author = {Meng{-}Fan Chang and
Kuei{-}Ann Wen and
Ding{-}Ming Kwai},
title = {Supply and Substrate Noise Tolerance Using Dynamic Tracking Clusters
in Configurable Memory Designs},
booktitle = {5th International Symposium on Quality of Electronic Design {(ISQED}
2004), 22-24 March 2004, San Jose, CA, {USA}},
pages = {297--302},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ISQED.2004.1283689},
doi = {10.1109/ISQED.2004.1283689},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/ChangWK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/ChangIO97,
author = {Meng{-}Fan Chang and
Mary Jane Irwin and
Robert Michael Owens},
title = {Power-Area Trade-Offs in Divided Word Line Memory Arrays},
journal = {J. Circuits Syst. Comput.},
volume = {7},
number = {1},
pages = {49--68},
year = {1997},
url = {https://doi.org/10.1142/S021812669700005X},
doi = {10.1142/S021812669700005X},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/ChangIO97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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