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ORCIDBibTeX records: Hideharu Amano
@article{DBLP:journals/tvlsi/UsamiYKASHB24,
author = {Kimiyoshi Usami and
Daiki Yokoyama and
Aika Kamei and
Hideharu Amano and
Kenta Suzuki and
Keizo Hiraga and
Kazuhiro Bessho},
title = {Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops
to Minimize Store Energy Under Process and Temperature Variations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {89--102},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3318468},
doi = {10.1109/TVLSI.2023.3318468},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/UsamiYKASHB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccel/AmanoI24,
author = {Hideharu Amano and
Kensuke Iizuka},
title = {Power analysis of an optical interconnected {FPGA} cluster for roadside
units},
booktitle = {{IEEE} International Conference on Consumer Electronics, {ICCE} 2024,
Las Vegas, NV, USA, January 6-8, 2024},
pages = {1--2},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ICCE59016.2024.10444498},
doi = {10.1109/ICCE59016.2024.10444498},
timestamp = {Fri, 08 Mar 2024 08:28:36 +0100},
biburl = {https://dblp.org/rec/conf/iccel/AmanoI24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/concurrency/YasudoNKMA23,
author = {Ryota Yasudo and
Koji Nakano and
Michihiro Koibuchi and
Hiroki Matsutani and
Hideharu Amano},
title = {Designing low-diameter interconnection networks with multi-ported
host-switch graphs},
journal = {Concurr. Comput. Pract. Exp.},
volume = {35},
number = {11},
year = {2023},
url = {https://doi.org/10.1002/cpe.6115},
doi = {10.1002/CPE.6115},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/concurrency/YasudoNKMA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/NiwaSAK23,
author = {Naoya Niwa and
Yoshiya Shikama and
Hideharu Amano and
Michihiro Koibuchi},
title = {A Compression Router for Low-Latency Network-on-Chip},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {106},
number = {2},
pages = {170--180},
year = {2023},
url = {https://doi.org/10.1587/transinf.2022edp7080},
doi = {10.1587/TRANSINF.2022EDP7080},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicetd/NiwaSAK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/WeiKAA23,
author = {Kaijie Wei and
Yuki Kuno and
Masatoshi Arai and
Hideharu Amano},
title = {RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High
Scalability},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {106},
number = {3},
pages = {337--348},
year = {2023},
url = {https://doi.org/10.1587/transinf.2022edp7131},
doi = {10.1587/TRANSINF.2022EDP7131},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicetd/WeiKAA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/FukushimaIA23,
author = {Yasuyu Fukushima and
Kensuke Iizuka and
Hideharu Amano},
title = {Parallel Implementation of {CNN} on Multi-FPGA Cluster},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {106},
number = {7},
pages = {1198--1208},
year = {2023},
url = {https://doi.org/10.1587/transinf.2022edp7175},
doi = {10.1587/TRANSINF.2022EDP7175},
timestamp = {Thu, 20 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicetd/FukushimaIA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/UllahAHIA23,
author = {M. M. Imdad Ullah and
Akram Ben Ahmed and
Kazuei Hironaka and
Kensuke Iizuka and
Hideharu Amano},
title = {A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {106},
number = {11},
pages = {1783--1795},
year = {2023},
url = {https://doi.org/10.1587/transinf.2022edp7230},
doi = {10.1587/TRANSINF.2022EDP7230},
timestamp = {Wed, 29 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicetd/UllahAHIA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/IizukaTKHA23,
author = {Kensuke Iizuka and
Haruna Takagi and
Aika Kamei and
Kazuei Hironaka and
Hideharu Amano},
title = {Power Analysis and Power Modeling of Directly-Connected {FPGA} Clusters},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {106},
number = {12},
pages = {1997--2005},
year = {2023},
url = {https://doi.org/10.1587/transinf.2023pap0009},
doi = {10.1587/TRANSINF.2023PAP0009},
timestamp = {Wed, 03 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicetd/IizukaTKHA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/KojimaOKA23,
author = {Takuya Kojima and
Hayate Okuhara and
Masaaki Kondo and
Hideharu Amano},
title = {A Scalable Body Bias Optimization Method Toward Low-Power CGRAs},
journal = {{IEEE} Micro},
volume = {43},
number = {1},
pages = {49--57},
year = {2023},
url = {https://doi.org/10.1109/MM.2022.3226739},
doi = {10.1109/MM.2022.3226739},
timestamp = {Tue, 31 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/micro/KojimaOKA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KameiAKYUHSB23,
author = {Aika Kamei and
Hideharu Amano and
Takuya Kojima and
Daiki Yokoyama and
Kimiyoshi Usami and
Keizo Hiraga and
Kenta Suzuki and
Kazuhiro Bessho},
title = {A Variation-Aware {MTJ} Store Energy Estimation Model for Edge Devices
With Verify-and-Retryable Nonvolatile Flip-Flops},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {532--542},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3237794},
doi = {10.1109/TVLSI.2023.3237794},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KameiAKYUHSB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/candar/FukushimaIA23,
author = {Yasuyu Fukushima and
Kensuke Iizuka and
Hideharu Amano},
title = {Parallel Implementation of Vision Transformer on a Multi-FPGA Cluster},
booktitle = {Eleventh International Symposium on Computing and Networking, {CANDAR}
2023, Matsue, Japan, November 28 - Dec. 1, 2023},
pages = {100--106},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/CANDAR60563.2023.00020},
doi = {10.1109/CANDAR60563.2023.00020},
timestamp = {Fri, 16 Feb 2024 13:45:14 +0100},
biburl = {https://dblp.org/rec/conf/candar/FukushimaIA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/QinWAN23,
author = {Ziquan Qin and
Kaijie Wei and
Hideharu Amano and
Kazuhiro Nakadai},
title = {Low power implementation of Geometric High-order Decorrelation-based
Source Separation on an {FPGA} board},
booktitle = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
2023, Tokyo, Japan, April 19-21, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/COOLCHIPS57690.2023.10121954},
doi = {10.1109/COOLCHIPS57690.2023.10121954},
timestamp = {Mon, 22 May 2023 21:13:40 +0200},
biburl = {https://dblp.org/rec/conf/coolchips/QinWAN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/WeiNAYM23,
author = {Kaijie Wei and
Ryohei Niwase and
Hideharu Amano and
Yoshiki Yamaguchi and
Takefumi Miyoshi},
title = {A state vector quantum simulator working on FPGAs with extensible
{SATA} storage},
booktitle = {International Conference on Field Programmable Technology, {ICFPT}
2023, Yokohama, Japan, December 12-14, 2023},
pages = {272--273},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICFPT59805.2023.00041},
doi = {10.1109/ICFPT59805.2023.00041},
timestamp = {Sat, 24 Feb 2024 20:42:47 +0100},
biburl = {https://dblp.org/rec/conf/fpt/WeiNAYM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/NiwaseHYWAM23,
author = {Ryohei Niwase and
Hikaru Harasawa and
Yoshiki Yamaguchi and
Kaijie Wei and
Hideharu Amano and
Takefumi Miyoshi},
title = {Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated
{SATA} storages},
booktitle = {International Conference on Field Programmable Technology, {ICFPT}
2023, Yokohama, Japan, December 12-14, 2023},
pages = {288--289},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICFPT59805.2023.00049},
doi = {10.1109/ICFPT59805.2023.00049},
timestamp = {Sat, 24 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/NiwaseHYWAM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/Amano23,
author = {Hideharu Amano},
title = {Efficient {FPGA} Implementation of Amoeba-inspired {SAT} Solver with
Feedback and Bounceback Control: Harnessing Variable-Level Parallelism
for Large-Scale Problem Solving in Edge Computing},
booktitle = {Proceedings of the 13th International Symposium on Highly Efficient
Accelerators and Reconfigurable Technologies, {HEART} 2023, Kusatsu,
Japan, June 14-16, 2023},
pages = {41--48},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3597031.3597052},
doi = {10.1145/3597031.3597052},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/heart/Amano23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/NiwaseHYWA23,
author = {Ryohei Niwase and
Hikaru Harasawa and
Yoshiki Yamaguchi and
Kaijie Wei and
Hideharu Amano},
title = {A cost/power efficient storage system with directly connected {FPGA}
and {SATA} disks},
booktitle = {16th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2023, Singapore, December 18-21, 2023},
pages = {51--58},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/MCSoC60832.2023.00016},
doi = {10.1109/MCSOC60832.2023.00016},
timestamp = {Fri, 09 Feb 2024 20:38:48 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/NiwaseHYWA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/InageIA23,
author = {Takumi Inage and
Kensuke Iizuka and
Hideharu Amano},
title = {Board Allocation Algorithm for the Resource Management System of FiC},
booktitle = {16th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2023, Singapore, December 18-21, 2023},
pages = {218--224},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/MCSoC60832.2023.00040},
doi = {10.1109/MCSOC60832.2023.00040},
timestamp = {Fri, 09 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/InageIA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sii/GulzarSINNAE23,
author = {Haris Gulzar and
Muhammad Shakeel and
Katsutoshi Itoyama and
Kazuhiro Nakadai and
Kenji Nishida and
Hideharu Amano and
Takeharu Eda},
title = {{FPGA} based Power-Efficient Edge Server to Accelerate Speech Interface
for Socially Assistive Robotics},
booktitle = {{IEEE/SICE} International Symposium on System Integration, {SII} 2023,
Atlanta, GA, USA, January 17-20, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/SII55687.2023.10039093},
doi = {10.1109/SII55687.2023.10039093},
timestamp = {Thu, 23 Feb 2023 17:35:09 +0100},
biburl = {https://dblp.org/rec/conf/sii/GulzarSINNAE23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/ShimizuIIHA22,
author = {Tomoki Shimizu and
Kohei Ito and
Kensuke Iizuka and
Kazuei Hironaka and
Hideharu Amano},
title = {The Implementation of a Hybrid Router and Dynamic Switching Algorithm
on a Multi-FPGA System},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {105-D},
number = {12},
pages = {2008--2018},
year = {2022},
url = {https://doi.org/10.1587/transinf.2022pap0009},
doi = {10.1587/TRANSINF.2022PAP0009},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicetd/ShimizuIIHA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/NiwaAK22,
author = {Naoya Niwa and
Hideharu Amano and
Michihiro Koibuchi},
title = {Boosting the Performance of Interconnection Networks by Selective
Data Compression},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {105-D},
number = {12},
pages = {2057--2065},
year = {2022},
url = {https://doi.org/10.1587/transinf.2022pap0005},
doi = {10.1587/TRANSINF.2022PAP0005},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicetd/NiwaAK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijnc/MaoWAKA22,
author = {Renzhi Mao and
Kaijie Wei and
Hideharu Amano and
Yuki Kuno and
Masatoshi Arai},
title = {Weighted Least Square Filter for Improving the Quality of Depth Map
on {FPGA}},
journal = {Int. J. Netw. Comput.},
volume = {12},
number = {2},
pages = {425--445},
year = {2022},
url = {http://www.ijnc.org/index.php/ijnc/article/view/291},
timestamp = {Mon, 21 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijnc/MaoWAKA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/ShikamaKMANFK22,
author = {Yoshiya Shikama and
Ryuta Kawano and
Hiroki Matsutani and
Hideharu Amano and
Yusuke Nagasaka and
Naoto Fukumoto and
Michihiro Koibuchi},
title = {A traffic-aware memory-cube network using bypassing},
journal = {Microprocess. Microsystems},
volume = {90},
pages = {104471},
year = {2022},
url = {https://doi.org/10.1016/j.micpro.2022.104471},
doi = {10.1016/J.MICPRO.2022.104471},
timestamp = {Wed, 17 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/ShikamaKMANFK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/KojimaOA22,
author = {Takuya Kojima and
Ayaka Ohwada and
Hideharu Amano},
title = {Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep
Learning},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {33},
number = {5},
pages = {1213--1230},
year = {2022},
url = {https://doi.org/10.1109/TPDS.2021.3107746},
doi = {10.1109/TPDS.2021.3107746},
timestamp = {Wed, 16 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tpds/KojimaOA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/IizukaTKHA22,
author = {Kensuke Iizuka and
Haruna Takagi and
Aika Kamei and
Kazuei Hironaka and
Hideharu Amano},
title = {Power Analysis of Directly-connected {FPGA} Clusters},
booktitle = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
2022, Tokyo, Japan, April 20-22, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/COOLCHIPS54332.2022.9772675},
doi = {10.1109/COOLCHIPS54332.2022.9772675},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/coolchips/IizukaTKHA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/KojimaOKA22,
author = {Takuya Kojima and
Hayate Okuhara and
Masaaki Kondo and
Hideharu Amano},
title = {Body Bias Control on a {CGRA} based on Convex Optimization},
booktitle = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
2022, Tokyo, Japan, April 20-22, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/COOLCHIPS54332.2022.9772708},
doi = {10.1109/COOLCHIPS54332.2022.9772708},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/coolchips/KojimaOKA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ItoYA22,
author = {Kohei Ito and
Ryota Yasudo and
Hideharu Amano},
title = {Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection
{STDM} Switches},
booktitle = {32nd International Conference on Field-Programmable Logic and Applications,
{FPL} 2022, Belfast, United Kingdom, August 29 - Sept. 2, 2022},
pages = {143--147},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/FPL57034.2022.00032},
doi = {10.1109/FPL57034.2022.00032},
timestamp = {Mon, 20 Feb 2023 17:38:16 +0100},
biburl = {https://dblp.org/rec/conf/fpl/ItoYA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KugaIA22,
author = {Morihiro Kuga and
Masahiro Iida and
Hideharu Amano},
title = {{FPL} Demo: An {FPGA-IP} Prototype Chip for {MEC} devices},
booktitle = {32nd International Conference on Field-Programmable Logic and Applications,
{FPL} 2022, Belfast, United Kingdom, August 29 - Sept. 2, 2022},
pages = {467},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/FPL57034.2022.00083},
doi = {10.1109/FPL57034.2022.00083},
timestamp = {Mon, 20 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/KugaIA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/WeiKAA22,
author = {Kaijie Wei and
Yuki Kuno and
Masatoshi Arai and
Hideharu Amano},
title = {RT-libSGM: An Implementation of a Real-time Stereo Matching System
on {FPGA}},
booktitle = {{HEART} 2022: International Symposium on Highly-Efficient Accelerators
and Reconfigurable Technologies, Tsukuba, Japan, June 9 - 10, 2022},
pages = {1--9},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3535044.3535045},
doi = {10.1145/3535044.3535045},
timestamp = {Mon, 20 Jun 2022 15:31:45 +0200},
biburl = {https://dblp.org/rec/conf/heart/WeiKAA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/ChenWNA22,
author = {Yuchen Chen and
Kaijie Wei and
Hiroaki Nishi and
Hideharu Amano},
title = {An Implementation of a 3D Image Filter for Motion Vector Generation
on an {FPGA} Board},
booktitle = {Tenth International Symposium on Computing and Networking, {CANDAR}
2022, Himeji, Japan, November 21-24, 2022},
pages = {83--89},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/CANDAR57322.2022.00018},
doi = {10.1109/CANDAR57322.2022.00018},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ic-nc/ChenWNA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/KawanoMKA22,
author = {Ryuta Kawano and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free
Interconnection Networks},
booktitle = {Tenth International Symposium on Computing and Networking, {CANDAR}
2022, Himeji, Japan, November 21-24, 2022},
pages = {117--123},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/CANDAR57322.2022.00023},
doi = {10.1109/CANDAR57322.2022.00023},
timestamp = {Mon, 13 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/KawanoMKA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/HirumaIA22,
author = {Aoi Hiruma and
Kensuke Iizuka and
Hideharu Amano},
title = {Toward a training of CNNs on a multi-FPGA system},
booktitle = {2022 Tenth International Symposium on Computing and Networking, {CANDAR}
2022 - Workshops, Himeji, Japan, November 21-24, 2022},
pages = {229--235},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/CANDARW57323.2022.00074},
doi = {10.1109/CANDARW57323.2022.00074},
timestamp = {Thu, 23 Mar 2023 08:30:32 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/HirumaIA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/HouWAN22,
author = {Zhongyang Hou and
Kaijie Wei and
Hideharu Amano and
Kazuhiro Nakadai},
title = {An {FPGA} off-loading of {HARK} sound source localization},
booktitle = {2022 Tenth International Symposium on Computing and Networking, {CANDAR}
2022 - Workshops, Himeji, Japan, November 21-24, 2022},
pages = {236--240},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/CANDARW57323.2022.00057},
doi = {10.1109/CANDARW57323.2022.00057},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/HouWAN22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/HuangWAOA22,
author = {Pengyu Huang and
Kaijie Wei and
Hideharu Amano and
Kaori Ohkoda and
Masashi Aono},
title = {Multi-board {FPGA} Implementation to Solve the Satisfiability Problem
for Multi-Agent Path Finding in Smart Factory},
booktitle = {2022 Tenth International Symposium on Computing and Networking, {CANDAR}
2022 - Workshops, Himeji, Japan, November 21-24, 2022},
pages = {406--410},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/CANDARW57323.2022.00034},
doi = {10.1109/CANDARW57323.2022.00034},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/HuangWAOA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/HironakaIA22,
author = {Kazuei Hironaka and
Kensuke Iizuka and
Hideharu Amano},
title = {A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA
Systems},
booktitle = {15th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2022, Penang, Malaysia, December 19-22, 2022},
pages = {45--52},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MCSoC57363.2022.00017},
doi = {10.1109/MCSOC57363.2022.00017},
timestamp = {Thu, 26 Jan 2023 11:35:12 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/HironakaIA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/YuqingNA22,
author = {Zhou Yuqing and
Naoya Niwa and
Hideharu Amano},
title = {Distance Aware Compression for Low Latency High Bandwidth Interconnection
Network},
booktitle = {15th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2022, Penang, Malaysia, December 19-22, 2022},
pages = {361--367},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MCSoC57363.2022.00063},
doi = {10.1109/MCSOC57363.2022.00063},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mcsoc/YuqingNA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/norcas/UsamiYKA22,
author = {Kimiyoshi Usami and
Daiki Yokoyama and
Aika Kamei and
Hideharu Amano},
editor = {Jari Nurmi and
Dag T. Wisland and
Snorre Aunet and
Kristian Kjelgaard},
title = {Optimal switching time to minimize store energy in MTJ-based flip-flops
under process and temperature variations},
booktitle = {{IEEE} Nordic Circuits and Systems Conference, NorCAS 2022, Oslo,
Norway, October 25-26, 2022},
pages = {1--7},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/NorCAS57515.2022.9934567},
doi = {10.1109/NORCAS57515.2022.9934567},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/norcas/UsamiYKA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdcat/ShikamaKA22,
author = {Yoshiya Shikama and
Michihiro Koibuchi and
Hideharu Amano},
editor = {Hiroyuki Takizawa and
Hong Shen and
Toshihiro Hanawa and
Jong Hyuk Park and
Hui Tian and
Ryusuke Egawa},
title = {A Hardware Trojan Exploiting Coherence Protocol on NoCs},
booktitle = {Parallel and Distributed Computing, Applications and Technologies
- 23rd International Conference, {PDCAT} 2022, Sendai, Japan, December
7-9, 2022, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {13798},
pages = {301--313},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-29927-8\_24},
doi = {10.1007/978-3-031-29927-8\_24},
timestamp = {Tue, 02 May 2023 15:08:25 +0200},
biburl = {https://dblp.org/rec/conf/pdcat/ShikamaKA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdp/OhwadaKA22,
author = {Ayaka Ohwada and
Takuya Kojima and
Hideharu Amano},
editor = {Arturo Gonz{\'{a}}lez{-}Escribano and
Jos{\'{e}} Daniel Garc{\'{\i}}a and
Massimo Torquati and
Amund Skavhaug},
title = {An efficient compilation of coarse-grained reconfigurable architectures
utilizing pre-optimized sub-graph mappings},
booktitle = {30th Euromicro International Conference on Parallel, Distributed and
Network-based Processing, {PDP} 2022, Valladolid, Spain, March 9-11,
2022},
pages = {1--9},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/PDP55904.2022.00010},
doi = {10.1109/PDP55904.2022.00010},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/pdp/OhwadaKA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/snpd/TakanoA22,
author = {Shigeyuki Takano and
Hideharu Amano},
title = {Reconfiguration Cost for Reconfigurable Computing Architectures},
booktitle = {23rd {ACIS} International Summer Virtual Conference on Software Engineering,
Artificial Intelligence, Networking and Parallel/Distributed Computing,
{SNPD} 2022 - Summer, Kyoto City, Japan, July 4-7, 2022},
pages = {62--67},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/SNPD-Summer57817.2022.00019},
doi = {10.1109/SNPD-SUMMER57817.2022.00019},
timestamp = {Fri, 03 Mar 2023 14:39:13 +0100},
biburl = {https://dblp.org/rec/conf/snpd/TakanoA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetc/IkezoeKA21,
author = {Takeharu Ikezoe and
Takuya Kojima and
Hideharu Amano},
title = {Recovering Faulty Non-Volatile Flip Flops for Coarse-Grained Reconfigurable
Architectures},
journal = {{IEICE} Trans. Electron.},
volume = {104-C},
number = {6},
pages = {215--225},
year = {2021},
url = {https://doi.org/10.1587/transele.2020lhp0002},
doi = {10.1587/TRANSELE.2020LHP0002},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicetc/IkezoeKA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/HironakaIYAA21,
author = {Kazuei Hironaka and
Kensuke Iizuka and
Miho Yamakura and
Akram Ben Ahmed and
Hideharu Amano},
title = {Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud)},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {104-D},
number = {8},
pages = {1321--1331},
year = {2021},
url = {https://doi.org/10.1587/transinf.2020edp7165},
doi = {10.1587/TRANSINF.2020EDP7165},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicetd/HironakaIYAA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/ItoIHHKA21,
author = {Kohei Ito and
Kensuke Iizuka and
Kazuei Hironaka and
Yao Hu and
Michihiro Koibuchi and
Hideharu Amano},
title = {Improving the Performance of Circuit-Switched Interconnection Network
for a Multi-FPGA System},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {104-D},
number = {12},
pages = {2029--2039},
year = {2021},
url = {https://doi.org/10.1587/transinf.2021pap0002},
doi = {10.1587/TRANSINF.2021PAP0002},
timestamp = {Thu, 12 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicetd/ItoIHHKA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/HondaWAA21,
author = {Koki Honda and
Kaijie Wei and
Masatoshi Arai and
Hideharu Amano},
title = {{CLAHE} Implementation and Evaluation on a Low-End {FPGA} Board by
High-Level Synthesis},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {104-D},
number = {12},
pages = {2048--2056},
year = {2021},
url = {https://doi.org/10.1587/transinf.2021pap0006},
doi = {10.1587/TRANSINF.2021PAP0006},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicetd/HondaWAA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/ItsuboKAM21,
author = {Tomoya Itsubo and
Michihiro Koibuchi and
Hideharu Amano and
Hiroki Matsutani},
title = {An FPGA-Based Optimizer Design for Distributed Deep Learning with
Multiple GPUs},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {104-D},
number = {12},
pages = {2057--2067},
year = {2021},
url = {https://doi.org/10.1587/transinf.2021pap0008},
doi = {10.1587/TRANSINF.2021PAP0008},
timestamp = {Thu, 12 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicetd/ItsuboKAM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/YamakuraTASA21,
author = {Miho Yamakura and
Ryousei Takano and
Akram Ben Ahmed and
Midori Sugaya and
Hideharu Amano},
title = {A Multi-Tenant Resource Management System for Multi-FPGA Systems},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {104-D},
number = {12},
pages = {2078--2088},
year = {2021},
url = {https://doi.org/10.1587/transinf.2021pap0005},
doi = {10.1587/TRANSINF.2021PAP0005},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicetd/YamakuraTASA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijnc/WeiHA21,
author = {Kaijie Wei and
Koki Honda and
Hideharu Amano},
title = {An implementation methodology for Neural Network on a Low-end {FPGA}
Board},
journal = {Int. J. Netw. Comput.},
volume = {11},
number = {2},
pages = {172--197},
year = {2021},
url = {http://www.ijnc.org/index.php/ijnc/article/view/249},
timestamp = {Tue, 27 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijnc/WeiHA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/YasudoCVLABG21,
author = {Ryota Yasudo and
Jos{\'{e}} Gabriel de Figueiredo Coutinho and
Ana Lucia Varbanescu and
Wayne Luk and
Hideharu Amano and
Tobias Becker and
Ce Guo},
title = {Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow
Platforms},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {3},
pages = {12:1--12:21},
year = {2021},
url = {https://doi.org/10.1145/3452742},
doi = {10.1145/3452742},
timestamp = {Wed, 01 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/YasudoCVLABG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/acit2/HironakaIA21,
author = {Kazuei Hironaka and
Kensuke Iizuka and
Hideharu Amano},
editor = {Hiroki Nomiya and
Yuhki Kitazono and
Takaaki Goto},
title = {Implementing VTA, a tensor accelerator on Flow-in-Cloud},
booktitle = {{ACIT} 2021: The 8th International Virtual Conference on Applied Computing
{\&} Information Technology, Kanazawa, Japan, June 20 - 22, 2021},
pages = {46--50},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3468081.3471121},
doi = {10.1145/3468081.3471121},
timestamp = {Tue, 26 Oct 2021 11:28:40 +0200},
biburl = {https://dblp.org/rec/conf/acit2/HironakaIA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/acit2/KawanoMKA21,
author = {Ryuta Kawano and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
editor = {Hiroki Nomiya and
Yuhki Kitazono and
Takaaki Goto},
title = {{GPU} Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree
Unweighted Regular Graph},
booktitle = {{ACIT} 2021: The 8th International Virtual Conference on Applied Computing
{\&} Information Technology, Kanazawa, Japan, June 20 - 22, 2021},
pages = {51--55},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3468081.3471122},
doi = {10.1145/3468081.3471122},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/acit2/KawanoMKA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KayashimaA21,
author = {Hideto Kayashima and
Hideharu Amano},
title = {{TCI} Tester: Tester for Through Chip Interface},
booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference,
Tokyo, Japan, January 18-21, 2021},
pages = {103--104},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3394885.3431660},
doi = {10.1145/3394885.3431660},
timestamp = {Mon, 03 May 2021 16:42:27 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KayashimaA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/ShimizuIIHA21,
author = {Tomoki Shimizu and
Kohei Ito and
Kensuke Iizuka and
Kazuei Hironaka and
Hideharu Amano},
title = {Hybrid Network of Packet Switching and {STDM} in a Multi-FPGA System},
booktitle = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
2021, Tokyo, Japan, April 14-16, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/COOLCHIPS52128.2021.9410322},
doi = {10.1109/COOLCHIPS52128.2021.9410322},
timestamp = {Tue, 04 May 2021 18:33:06 +0200},
biburl = {https://dblp.org/rec/conf/coolchips/ShimizuIIHA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/edge2/NatsuhoOAS21,
author = {Sannomiya Natsuho and
Takeshi Ohkawa and
Hideharu Amano and
Midori Sugaya},
editor = {Liang{-}Jie Zhang},
title = {Power Consumption Reduction Method and Edge Offload Server for Multiple
Robots},
booktitle = {Edge Computing - {EDGE} 2021 - 5th International Conference, Held
as Part of the Services Conference Federation, {SCF} 2021, Virtual
Event, December 10-14, 2021, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {12990},
pages = {1--19},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-030-96504-4\_1},
doi = {10.1007/978-3-030-96504-4\_1},
timestamp = {Wed, 09 Mar 2022 14:35:18 +0100},
biburl = {https://dblp.org/rec/conf/edge2/NatsuhoOAS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/YanAAOFSK21,
author = {Ying Jie Yan and
Hideharu Amano and
Masashi Aono and
Kaori Ohkoda and
Shingo Fukuda and
Kenta Saito and
Seiya Kasai},
title = {Resource-saving {FPGA} Implementation of the Satisfiability Problem
Solver: AmoebaSATslim},
booktitle = {International Conference on Field-Programmable Technology, {(IC)FPT}
2021, Auckland, New Zealand, December 6-10, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICFPT52863.2021.9609882},
doi = {10.1109/ICFPT52863.2021.9609882},
timestamp = {Fri, 03 Dec 2021 17:36:20 +0100},
biburl = {https://dblp.org/rec/conf/fpt/YanAAOFSK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/SuzukiTWA21,
author = {Hiroaki Suzuki and
Wataru Takahashi and
Kazutoshi Wakabayashi and
Hideharu Amano},
editor = {Christian Plessl and
Paul Chow and
Marco Platzner},
title = {A programming environment for multi-FPGA systems based on CyberWorkBench:
an integrated design tool},
booktitle = {{HEART} '21: 11th International Symposium on Highly Efficient Accelerators
and Reconfigurable Technologies, Virtual Event, Germany, 21-23 June,
2021},
pages = {5:1--5:6},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3468044.3468049},
doi = {10.1145/3468044.3468049},
timestamp = {Wed, 04 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/heart/SuzukiTWA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/NiwaAK21,
author = {Naoya Niwa and
Hideharu Amano and
Michihiro Koibuchi},
title = {Low-Latency High-Bandwidth Interconnection Networks by Selective Packet
Compression},
booktitle = {Ninth International Symposium on Computing and Networking, {CANDAR}
2021, Matsue, Japan, November 23-26, 2021},
pages = {56--64},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/CANDAR53791.2021.00015},
doi = {10.1109/CANDAR53791.2021.00015},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ic-nc/NiwaAK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/InageHIIFNA21,
author = {Takumi Inage and
Kazuei Hironaka and
Kensuke Iizuka and
Kohei Ito and
Yasuyu Fukushima and
Mitaro Namiki and
Hideharu Amano},
title = {{M-KUBOS/PYNQ} Cluster for multi-access edge computing},
booktitle = {Ninth International Symposium on Computing and Networking, {CANDAR}
2021, Matsue, Japan, November 23-26, 2021},
pages = {95--101},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/CANDAR53791.2021.00020},
doi = {10.1109/CANDAR53791.2021.00020},
timestamp = {Wed, 29 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/InageHIIFNA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/KayashimaA21,
author = {Hideto Kayashima and
Hideharu Amano},
title = {Analysis of Resistance Distribution and Voltage Drop in Chips with
Inductive Coupling Wireless Communication Interface},
booktitle = {Ninth International Symposium on Computing and Networking, {CANDAR}
2021 - Workshops, Matsue, Japan, 23-26 November 2021},
pages = {292--296},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/CANDARW53999.2021.00055},
doi = {10.1109/CANDARW53999.2021.00055},
timestamp = {Fri, 18 Feb 2022 10:36:44 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/KayashimaA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/MaoWAKA21,
author = {Renzhi Mao and
Kaijie Wei and
Hideharu Amano and
Yuki Kuno and
Masatoshi Arai},
title = {Weight Least Square Filter for Improving the Quality of Depth Map
on {FPGA}},
booktitle = {Ninth International Symposium on Computing and Networking, {CANDAR}
2021 - Workshops, Matsue, Japan, 23-26 November 2021},
pages = {297--300},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/CANDARW53999.2021.00056},
doi = {10.1109/CANDARW53999.2021.00056},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ic-nc/MaoWAKA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/FukushimaIA21,
author = {Yasuyu Fukushima and
Kensuke Iizuka and
Hideharu Amano},
title = {Parallel Implementation of {CNN} on Multi-FPGA Cluster},
booktitle = {14th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2021, Singapore, Singapore, December 20-23,
2021},
pages = {77--83},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/MCSoC51149.2021.00019},
doi = {10.1109/MCSOC51149.2021.00019},
timestamp = {Fri, 11 Feb 2022 09:29:47 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/FukushimaIA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/KameiKAYMUHSB21,
author = {Aika Kamei and
Takuya Kojima and
Hideharu Amano and
Daiki Yokoyama and
Hisato Miyauchi and
Kimiyoshi Usami and
Keizo Hiraga and
Kenta Suzuki and
Kazuhiro Bessho},
title = {Energy saving in a multi-context coarse grained reconfigurable array
with non-volatile flip-flops},
booktitle = {14th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2021, Singapore, Singapore, December 20-23,
2021},
pages = {273--280},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/MCSoC51149.2021.00047},
doi = {10.1109/MCSOC51149.2021.00047},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mcsoc/KameiKAYMUHSB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdp/NiwaSAK21,
author = {Naoya Niwa and
Yoshiya Shikama and
Hideharu Amano and
Michihiro Koibuchi},
title = {A Case for Low-Latency Network-on-Chip using Compression Routers},
booktitle = {29th Euromicro International Conference on Parallel, Distributed and
Network-Based Processing, {PDP} 2021, Valladolid, Spain, March 10-12,
2021},
pages = {134--142},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/PDP52278.2021.00029},
doi = {10.1109/PDP52278.2021.00029},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/pdp/NiwaSAK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdp/ShikamaKMANFK21,
author = {Yoshiya Shikama and
Ryuta Kawano and
Hiroki Matsutani and
Hideharu Amano and
Yusuke Nagasaka and
Naoto Fukumoto and
Michihiro Koibuchi},
title = {Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths},
booktitle = {29th Euromicro International Conference on Parallel, Distributed and
Network-Based Processing, {PDP} 2021, Valladolid, Spain, March 10-12,
2021},
pages = {143--147},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/PDP52278.2021.00030},
doi = {10.1109/PDP52278.2021.00030},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/pdp/ShikamaKMANFK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KawanoYMKA20,
author = {Ryuta Kawano and
Ryota Yasudo and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular
Networks},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {103-D},
number = {1},
pages = {101--110},
year = {2020},
url = {http://search.ieice.org/bin/summary.php?id=e103-d\_1\_101},
doi = {10.1587/TRANSINF.2018EDP7367},
timestamp = {Mon, 06 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/KawanoYMKA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/SunA20,
author = {Yuxi Sun and
Hideharu Amano},
title = {FiC-RNN: {A} Multi-FPGA Acceleration Framework for Deep Recurrent
Neural Networks},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {103-D},
number = {12},
pages = {2457--2462},
year = {2020},
url = {https://doi.org/10.1587/transinf.2020PAP0003},
doi = {10.1587/TRANSINF.2020PAP0003},
timestamp = {Mon, 07 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicetd/SunA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/KawanoYMKA20,
author = {Ryuta Kawano and
Ryota Yasudo and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {Traffic-Independent Multi-Path Routing for High-Throughput Data Center
Networks},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {103-D},
number = {12},
pages = {2471--2479},
year = {2020},
url = {https://doi.org/10.1587/transinf.2020PAP0005},
doi = {10.1587/TRANSINF.2020PAP0005},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicetd/KawanoYMKA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/NishioPSAM20,
author = {Shin Nishio and
Yulu Pan and
Takahiko Satoh and
Hideharu Amano and
Rodney Van Meter},
title = {Extracting Success from IBM's 20-Qubit Machines Using Error-Aware
Compilation},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {16},
number = {3},
pages = {32:1--32:25},
year = {2020},
url = {https://doi.org/10.1145/3386162},
doi = {10.1145/3386162},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jetc/NishioPSAM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KojimaDA20,
author = {Takuya Kojima and
Nguyen Anh Vu Doan and
Hideharu Amano},
title = {GenMap: {A} Genetic Algorithmic Approach for Optimizing Spatial Mapping
of Coarse-Grained Reconfigurable Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2383--2396},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3009225},
doi = {10.1109/TVLSI.2020.3009225},
timestamp = {Tue, 01 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KojimaDA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/UllahAA20,
author = {M. M. Imdad Ullah and
Akram Ben Ahmed and
Hideharu Amano},
editor = {Fernando Rinc{\'{o}}n and
Jes{\'{u}}s Barba and
Hayden Kwok{-}Hay So and
Pedro C. Diniz and
Juli{\'{a}}n Caba},
title = {Implementation of FM-Index Based Pattern Search on a Multi-FPGA System},
booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications
- 16th International Symposium, {ARC} 2020, Toledo, Spain, April 1-3,
2020, Proceedings [postponed]},
series = {Lecture Notes in Computer Science},
volume = {12083},
pages = {376--391},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-44534-8\_28},
doi = {10.1007/978-3-030-44534-8\_28},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arc/UllahAA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/UsamiAAIHSK20,
author = {Kimiyoshi Usami and
Sosuke Akiba and
Hideharu Amano and
Takeharu Ikezoe and
Keizo Hiraga and
Kenta Suzuki and
Yasuo Kanda},
title = {Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step
Store Control for Energy Minimization},
booktitle = {2020 {IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
2020, Kokubunji, Japan, April 15-17, 2020},
pages = {1--3},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/COOLCHIPS49199.2020.9097630},
doi = {10.1109/COOLCHIPS49199.2020.9097630},
timestamp = {Sat, 06 Jun 2020 15:00:53 +0200},
biburl = {https://dblp.org/rec/conf/coolchips/UsamiAAIHSK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/KawanoMA20,
author = {Ryuta Kawano and
Hiroki Matsutani and
Hideharu Amano},
title = {Layout-Oriented Low-Diameter Topology for {HPC} Interconnection Networks},
booktitle = {Eighth International Symposium on Computing and Networking Workshops,
{CANDAR} 2020 Workshops, Naha, Japan, November 24-27, 2020},
pages = {93--99},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/CANDARW51189.2020.00029},
doi = {10.1109/CANDARW51189.2020.00029},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ic-nc/KawanoMA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/LealSAO20,
author = {Daniel Pinheiro Leal and
Midori Sugaya and
Hideharu Amano and
Takeshi Ohkawa},
title = {{FPGA} Acceleration of ROS2-Based Reinforcement Learning Agents},
booktitle = {Eighth International Symposium on Computing and Networking Workshops,
{CANDAR} 2020 Workshops, Naha, Japan, November 24-27, 2020},
pages = {106--112},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/CANDARW51189.2020.00031},
doi = {10.1109/CANDARW51189.2020.00031},
timestamp = {Wed, 03 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/LealSAO20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/OrsztynowiczAKM20,
author = {Manfred Orsztynowicz and
Hideharu Amano and
Kenichi Kubota and
Takaaki Miyajima},
title = {Exploiting temporal parallelism in particle-based incompressive fluid
simulation on {FPGA}},
booktitle = {Eighth International Symposium on Computing and Networking, {CANDAR}
2020, Naha, Japan, November 24-27, 2020},
pages = {195--201},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/CANDAR51075.2020.00034},
doi = {10.1109/CANDAR51075.2020.00034},
timestamp = {Fri, 16 Apr 2021 10:58:06 +0200},
biburl = {https://dblp.org/rec/conf/ic-nc/OrsztynowiczAKM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/ItoIHHKA20,
author = {Kohei Ito and
Kensuke Iizuka and
Kazuei Hironaka and
Yao Hu and
Michihiro Koibuchi and
Hideharu Amano},
title = {Implementing a Multi-ejection Switch and Making the Use of Multiple
Lanes in a Circuit-switched Multi-FPGA System},
booktitle = {Eighth International Symposium on Computing and Networking Workshops,
{CANDAR} 2020 Workshops, Naha, Japan, November 24-27, 2020},
pages = {211--217},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/CANDARW51189.2020.00049},
doi = {10.1109/CANDARW51189.2020.00049},
timestamp = {Wed, 03 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/ItoIHHKA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/WeiHA20,
author = {Kaijie Wei and
Koki Honda and
Hideharu Amano},
title = {An implementation methodology for Neural Network on a Low-end {FPGA}
Board},
booktitle = {Eighth International Symposium on Computing and Networking, {CANDAR}
2020, Naha, Japan, November 24-27, 2020},
pages = {228--234},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/CANDAR51075.2020.00039},
doi = {10.1109/CANDAR51075.2020.00039},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ic-nc/WeiHA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/YamauchiAHIA20,
author = {Yugo Yamauchi and
Akram Ben Ahmed and
Kazuei Hironaka and
Kensuke Iizuka and
Hideharu Amano},
title = {Horizontal division of deep learning applications with all-to-all
communication on a multi-FPGA system},
booktitle = {Eighth International Symposium on Computing and Networking Workshops,
{CANDAR} 2020 Workshops, Naha, Japan, November 24-27, 2020},
pages = {277--281},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/CANDARW51189.2020.00060},
doi = {10.1109/CANDARW51189.2020.00060},
timestamp = {Wed, 03 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/YamauchiAHIA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/HondaWAA20,
author = {Koki Honda and
Kaijie Wei and
Masatoshi Arai and
Hideharu Amano},
title = {{CLAHE} implementation on a low-end {FPGA} board by high-level synthesis},
booktitle = {Eighth International Symposium on Computing and Networking Workshops,
{CANDAR} 2020 Workshops, Naha, Japan, November 24-27, 2020},
pages = {282--285},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/CANDARW51189.2020.00061},
doi = {10.1109/CANDARW51189.2020.00061},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ic-nc/HondaWAA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icfpt/LealSAO20,
author = {Daniel Pinheiro Leal and
Midori Sugaya and
Hideharu Amano and
Takeshi Ohkawa},
title = {Automated Integration of High-Level Synthesis {FPGA} Modules with
{ROS2} Systems},
booktitle = {International Conference on Field-Programmable Technology, {(IC)FPT}
2020, Maui, HI, USA, December 9-11, 2020},
pages = {292--293},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICFPT51103.2020.00052},
doi = {10.1109/ICFPT51103.2020.00052},
timestamp = {Tue, 11 May 2021 10:41:35 +0200},
biburl = {https://dblp.org/rec/conf/icfpt/LealSAO20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/IizukaIHA20,
author = {Kensuke Iizuka and
Kohei Ito and
Kazuei Hironaka and
Hideharu Amano},
title = {A Method of Partitioning Convolutional Layer to Multiple FPGAs},
booktitle = {International SoC Design Conference, {ISOCC} 2020, Yeosu, South Korea,
October 21-24, 2020},
pages = {25--26},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISOCC50952.2020.9332929},
doi = {10.1109/ISOCC50952.2020.9332929},
timestamp = {Fri, 12 Feb 2021 11:57:12 +0100},
biburl = {https://dblp.org/rec/conf/isocc/IizukaIHA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdp/ItsuboKAM20,
author = {Tomoya Itsubo and
Michihiro Koibuchi and
Hideharu Amano and
Hiroki Matsutani},
title = {Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE
Switch},
booktitle = {28th Euromicro International Conference on Parallel, Distributed and
Network-Based Processing, {PDP} 2020, V{\"{a}}ster{\aa}s, Sweden,
March 11-13, 2020},
pages = {102--109},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/PDP50117.2020.00022},
doi = {10.1109/PDP50117.2020.00022},
timestamp = {Tue, 19 May 2020 14:16:27 +0200},
biburl = {https://dblp.org/rec/conf/pdp/ItsuboKAM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KojimaA19,
author = {Takuya Kojima and
Hideharu Amano},
title = {A Fine-Grained Multicasting of Configuration Data for Coarse-Grained
Reconfigurable Architectures},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {102-D},
number = {7},
pages = {1247--1256},
year = {2019},
url = {https://doi.org/10.1587/transinf.2018EDP7336},
doi = {10.1587/TRANSINF.2018EDP7336},
timestamp = {Thu, 21 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/KojimaA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/YasudoKNMA19,
author = {Ryota Yasudo and
Michihiro Koibuchi and
Koji Nakano and
Hiroki Matsutani and
Hideharu Amano},
title = {Designing High-Performance Interconnection Networks with Host-Switch
Graphs},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {30},
number = {2},
pages = {315--330},
year = {2019},
url = {https://doi.org/10.1109/TPDS.2018.2864286},
doi = {10.1109/TPDS.2018.2864286},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/YasudoKNMA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/TokusashiMA19,
author = {Yuta Tokusashi and
Hiroki Matsutani and
Hideharu Amano},
title = {Key-value Store Chip Design for Low Power Consumption},
booktitle = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
2019, Yokohama, Japan, April 17-19, 2019},
pages = {1--3},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/CoolChips.2019.8721352},
doi = {10.1109/COOLCHIPS.2019.8721352},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/coolchips/TokusashiMA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/YamauchiMA19,
author = {Yugo Yamauchi and
Kazusa Musha and
Hideharu Amano},
title = {Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud},
booktitle = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
2019, Yokohama, Japan, April 17-19, 2019},
pages = {1--3},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/CoolChips.2019.8721333},
doi = {10.1109/COOLCHIPS.2019.8721333},
timestamp = {Tue, 04 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/coolchips/YamauchiMA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KoibuchiLTNMAC19,
author = {Michihiro Koibuchi and
Lambert Leong and
Tomohiro Totoki and
Naoya Niwa and
Hiroki Matsutani and
Hideharu Amano and
Henri Casanova},
title = {Sparse 3-D NoCs with Inductive Coupling},
booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019,
{DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019},
pages = {49},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3316781.3317913},
doi = {10.1145/3316781.3317913},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/KoibuchiLTNMAC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KojimaAMA19,
author = {Takuya Kojima and
Naoki Ando and
Yusuke Matsushita and
Hideharu Amano},
editor = {Ioannis Sourdis and
Christos{-}Savvas Bouganis and
Carlos {\'{A}}lvarez and
Leonel Antonio Toledo D{\'{\i}}az and
Pedro Valero{-}Lara and
Xavier Martorell},
title = {Demonstration of Low Power Stream Processing Using a Variable Pipelined
{CGRA}},
booktitle = {29th International Conference on Field Programmable Logic and Applications,
{FPL} 2019, Barcelona, Spain, September 8-12, 2019},
pages = {411--412},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/FPL.2019.00071},
doi = {10.1109/FPL.2019.00071},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/KojimaAMA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/HironakaIAUYSYH19,
author = {Kazuei Hironaka and
Kensuke Iizuka and
Akram Ben Ahmed and
M. M. Imdad Ullah and
Yugo Yamauchi and
Yuxi Sun and
Miho Yamakura and
Aoi Hiruma and
Hideharu Amano},
editor = {Ioannis Sourdis and
Christos{-}Savvas Bouganis and
Carlos {\'{A}}lvarez and
Leonel Antonio Toledo D{\'{\i}}az and
Pedro Valero{-}Lara and
Xavier Martorell},
title = {Demonstration of Flow-in-Cloud: {A} Multi-FPGA System},
booktitle = {29th International Conference on Field Programmable Logic and Applications,
{FPL} 2019, Barcelona, Spain, September 8-12, 2019},
pages = {417--418},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/FPL.2019.00074},
doi = {10.1109/FPL.2019.00074},
timestamp = {Mon, 07 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/HironakaIAUYSYH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/NodaOIMFA19,
author = {Hiroyuki Noda and
Manfred Orsztynowicz and
Kensuke Iizuka and
Takaaki Miyajima and
Naoyuki Fujita and
Hideharu Amano},
title = {An ARM-based heterogeneous {FPGA} accelerator for Hall thruster simulation},
booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
Japan, June 6-7, 2019},
pages = {9:1--9:6},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3337801.3337812},
doi = {10.1145/3337801.3337812},
timestamp = {Sun, 14 Jul 2019 18:04:14 +0200},
biburl = {https://dblp.org/rec/conf/heart/NodaOIMFA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/YamakuraHAMA19,
author = {Miho Yamakura and
Kazuei Hironaka and
Keita Azegami and
Kazusa Musha and
Hideharu Amano},
title = {The Evaluation of Partial Reconfiguration for a Multi-board {FPGA}
System FiCSW},
booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
Japan, June 6-7, 2019},
pages = {15:1--15:4},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3337801.3337805},
doi = {10.1145/3337801.3337805},
timestamp = {Sun, 14 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/heart/YamakuraHAMA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/SunAA19,
author = {Yuxi Sun and
Akram Ben Ahmed and
Hideharu Amano},
title = {Acceleration of Deep Recurrent Neural Networks with an {FPGA} cluster},
booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
Japan, June 6-7, 2019},
pages = {18:1--18:4},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3337801.3337804},
doi = {10.1145/3337801.3337804},
timestamp = {Mon, 07 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/heart/SunAA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/KawanoMA19,
author = {Ryuta Kawano and
Hiroki Matsutani and
Hideharu Amano},
title = {Deadlock-Free Layered Routing for Infiniband Networks},
booktitle = {Seventh International Symposium on Computing and Networking Workshops,
{CANDAR} 2019 Workshops, Nagasaki, Japan, November 26-29, 2019},
pages = {84--90},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/CANDARW.2019.00023},
doi = {10.1109/CANDARW.2019.00023},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ic-nc/KawanoMA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/KayashimaKOSA19,
author = {Hideto Kayashima and
Takuya Kojima and
Hayate Okuhara and
Tsunaaki Shidei and
Hideharu Amano},
title = {Real Chip Performance Evaluation on Through Chip Interface {IP} for
Renesas {SOTB} 65nm Process},
booktitle = {Seventh International Symposium on Computing and Networking Workshops,
{CANDAR} 2019 Workshops, Nagasaki, Japan, November 26-29, 2019},
pages = {269--274},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/CANDARW.2019.00054},
doi = {10.1109/CANDARW.2019.00054},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/KayashimaKOSA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/KazamiA19,
author = {Ryosuke Kazami and
Hideharu Amano},
title = {A Rapid Optimization Method for Visual Indirect {SLAM} Using a Subset
of Feature Points},
booktitle = {Seventh International Symposium on Computing and Networking Workshops,
{CANDAR} 2019 Workshops, Nagasaki, Japan, November 26-29, 2019},
pages = {275--279},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/CANDARW.2019.00055},
doi = {10.1109/CANDARW.2019.00055},
timestamp = {Tue, 04 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/KazamiA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/OkamotoA19,
author = {Yasuaki Okamoto and
Hideharu Amano},
title = {Acceleration of {ART} Algorithm on an {FPGA} Board with Xilinx SDAccel},
booktitle = {Seventh International Symposium on Computing and Networking Workshops,
{CANDAR} 2019 Workshops, Nagasaki, Japan, November 26-29, 2019},
pages = {280--284},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/CANDARW.2019.00056},
doi = {10.1109/CANDARW.2019.00056},
timestamp = {Tue, 04 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/OkamotoA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icfpt/IkezoeKA19,
author = {Takeharu Ikezoe and
Takuya Kojima and
Hideharu Amano},
title = {A Coarse-Grained Reconfigurable Architecture with a Fault Tolerant
Non-Volatile Configurable Memory},
booktitle = {International Conference on Field-Programmable Technology, {FPT} 2019,
Tianjin, China, December 9-13, 2019},
pages = {81--89},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ICFPT47387.2019.00018},
doi = {10.1109/ICFPT47387.2019.00018},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icfpt/IkezoeKA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/OkuharaKA19,
author = {Hayate Okuhara and
Ryosuke Kazami and
Hideharu Amano},
title = {A System Delay Monitor Exploiting Automatic Cell-Based Design Flow
and Post-Silicon Calibration},
booktitle = {13th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2019, Singapore, Singapore, October 1-4, 2019},
pages = {32--37},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/MCSoC.2019.00012},
doi = {10.1109/MCSOC.2019.00012},
timestamp = {Tue, 26 Nov 2019 20:28:29 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/OkuharaKA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/HondaWA19,
author = {Koki Honda and
Kaijie Wei and
Hideharu Amano},
title = {FPGA/Python Co-Design for Lane Line Detection on a {PYNQ-Z1} Board},
booktitle = {13th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2019, Singapore, Singapore, October 1-4, 2019},
pages = {53--60},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/MCSoC.2019.00015},
doi = {10.1109/MCSOC.2019.00015},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mcsoc/HondaWA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/TerashimaKOMASK19,
author = {Sayaka Terashima and
Takuya Kojima and
Hayate Okuhara and
Kazusa Musha and
Hideharu Amano and
Ryuichi Sakamoto and
Masaaki Kondo and
Mitaro Namiki},
title = {A Preliminary Evaluation of Building Block Computing Systems},
booktitle = {13th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2019, Singapore, Singapore, October 1-4, 2019},
pages = {312--319},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/MCSoC.2019.00051},
doi = {10.1109/MCSOC.2019.00051},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/TerashimaKOMASK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/AzegamiMHAKHA19,
author = {Keita Azegami and
Kazusa Musha and
Kazuei Hironaka and
Akram Ben Ahmed and
Michihiro Koibuchi and
Yao Hu and
Hideharu Amano},
title = {A {STDM} (Static Time Division Multiplexing) Switch on a Multi-FPGA
System},
booktitle = {13th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2019, Singapore, Singapore, October 1-4, 2019},
pages = {328--333},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/MCSoC.2019.00053},
doi = {10.1109/MCSOC.2019.00053},
timestamp = {Tue, 26 Nov 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/AzegamiMHAKHA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/recosoc/KojimaA19,
author = {Takuya Kojima and
Hideharu Amano},
title = {Refinements in Data Manipulation Method for Coarse Grained Reconfigurable
Architectures},
booktitle = {14th International Symposium on Reconfigurable Communication-centric
Systems-on-Chip, ReCoSoC 2019, York, United Kingdom, July 1-3, 2019},
pages = {113--120},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ReCoSoC48741.2019.9034924},
doi = {10.1109/RECOSOC48741.2019.9034924},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/recosoc/KojimaA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/snpd/HironakaAA19,
author = {Kazuei Hironaka and
Akram Ben Ahmed and
Hideharu Amano},
editor = {Masahide Nakamura and
Hiroaki Hirata and
Takayuki Ito and
Takanobu Otsuka and
Shun Okuhara},
title = {Multi-FPGA Management on Flow-in-Cloud Prototype System},
booktitle = {20th {IEEE/ACIS} International Conference on Software Engineering,
Artificial Intelligence, Networking and Parallel/Distributed Computing,
{SNPD} 2019, Toyama, Japan, July 8-11, 2019},
pages = {443--448},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SNPD.2019.8935738},
doi = {10.1109/SNPD.2019.8935738},
timestamp = {Tue, 07 Sep 2021 18:19:39 +0200},
biburl = {https://dblp.org/rec/conf/snpd/HironakaAA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1903-10963,
author = {Shin Nishio and
Yulu Pan and
Takahiko Satoh and
Hideharu Amano and
Rodney Van Meter},
title = {Extracting Success from IBM's 20-Qubit Machines Using Error-Aware
Compilation},
journal = {CoRR},
volume = {abs/1903.10963},
year = {2019},
url = {http://arxiv.org/abs/1903.10963},
eprinttype = {arXiv},
eprint = {1903.10963},
timestamp = {Tue, 02 Apr 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1903-10963.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TorresOYA18,
author = {Carlos Cesar Cortes Torres and
Hayate Okuhara and
Nobuyuki Yamasaki and
Hideharu Amano},
title = {Analysis of Body Bias Control Using Overhead Conditions for Real Time
Systems: {A} Practical Approach},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {101-D},
number = {4},
pages = {1116--1125},
year = {2018},
url = {https://doi.org/10.1587/transinf.2017EDP7258},
doi = {10.1587/TRANSINF.2017EDP7258},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/TorresOYA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KojimaAODA18,
author = {Takuya Kojima and
Naoki Ando and
Hayate Okuhara and
Ng. Anh Vu Doan and
Hideharu Amano},
title = {Optimization of Body Biasing for Variable Pipelined Coarse-Grained
Reconfigurable Architectures},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {101-D},
number = {6},
pages = {1532--1540},
year = {2018},
url = {https://doi.org/10.1587/transinf.2017EDP7308},
doi = {10.1587/TRANSINF.2017EDP7308},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KojimaAODA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/MitsuzukaKAM18,
author = {Koya Mitsuzuka and
Michihiro Koibuchi and
Hideharu Amano and
Hiroki Matsutani},
title = {Proxy Responses by FPGA-Based Switch for MapReduce Stragglers},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {101-D},
number = {9},
pages = {2258--2268},
year = {2018},
url = {https://doi.org/10.1587/transinf.2017EDP7287},
doi = {10.1587/TRANSINF.2017EDP7287},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/MitsuzukaKAM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijnc/NomuraMKMKA18,
author = {Akio Nomura and
Yusuke Matsushita and
Junichiro Kadomoto and
Hiroki Matsutani and
Tadahiro Kuroda and
Hideharu Amano},
title = {Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip
Interface},
journal = {Int. J. Netw. Comput.},
volume = {8},
number = {1},
pages = {124--139},
year = {2018},
url = {http://www.ijnc.org/index.php/ijnc/article/view/174},
timestamp = {Tue, 16 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijnc/NomuraMKMKA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/OkuharaAA18,
author = {Hayate Okuhara and
Akram Ben Ahmed and
Hideharu Amano},
title = {Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power
{VLSI} Systems},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {65-I},
number = {10},
pages = {3241--3254},
year = {2018},
url = {https://doi.org/10.1109/TCSI.2018.2811504},
doi = {10.1109/TCSI.2018.2811504},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/OkuharaAA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tmscs/AzegamiOA18,
author = {Keita Azegami and
Hayate Okuhara and
Hideharu Amano},
title = {Body Bias Control for Renewable Energy Source with a High Inner Resistance},
journal = {{IEEE} Trans. Multi Scale Comput. Syst.},
volume = {4},
number = {4},
pages = {605--612},
year = {2018},
url = {https://doi.org/10.1109/TMSCS.2018.2827980},
doi = {10.1109/TMSCS.2018.2827980},
timestamp = {Wed, 02 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tmscs/AzegamiOA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OkuharaAKA18,
author = {Hayate Okuhara and
Akram Ben Ahmed and
Johannes Maximilian K{\"{u}}hn and
Hideharu Amano},
title = {Asymmetric Body Bias Control With Low-Power {FD-SOI} Technologies:
Modeling and Power Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {7},
pages = {1254--1267},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2812893},
doi = {10.1109/TVLSI.2018.2812893},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OkuharaAKA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/MushaKA18,
author = {Kazusa Musha and
Tomohiro Kudoh and
Hideharu Amano},
editor = {Nikolaos S. Voros and
Michael H{\"{u}}bner and
Georgios Keramidas and
Diana Goehringer and
Christos P. Antonopoulos and
Pedro C. Diniz},
title = {Deep Learning on High Performance {FPGA} Switching Boards: Flow-in-Cloud},
booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications
- 14th International Symposium, {ARC} 2018, Santorini, Greece, May
2-4, 2018, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10824},
pages = {43--54},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-319-78890-6\_4},
doi = {10.1007/978-3-319-78890-6\_4},
timestamp = {Wed, 28 Apr 2021 16:06:57 +0200},
biburl = {https://dblp.org/rec/conf/arc/MushaKA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/HironakaDA18,
author = {Kazuei Hironaka and
Ng. Anh Vu Doan and
Hideharu Amano},
editor = {Nikolaos S. Voros and
Michael H{\"{u}}bner and
Georgios Keramidas and
Diana Goehringer and
Christos P. Antonopoulos and
Pedro C. Diniz},
title = {Towards an Optimized Multi {FPGA} Architecture with {STDM} Network:
{A} Preliminary Study},
booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications
- 14th International Symposium, {ARC} 2018, Santorini, Greece, May
2-4, 2018, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10824},
pages = {142--150},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-319-78890-6\_12},
doi = {10.1007/978-3-319-78890-6\_12},
timestamp = {Thu, 26 Apr 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arc/HironakaDA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/KazamiOA18,
author = {Ryosuke Kazami and
Hayate Okuhara and
Hideharu Amano},
title = {Design automation methodology of a critical path monitor for adaptive
voltage controls},
booktitle = {2018 {IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
2018, Yokohama, Japan, April 18-20, 2018},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/CoolChips.2018.8373073},
doi = {10.1109/COOLCHIPS.2018.8373073},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/KazamiOA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/AkagicBTHNA18,
author = {Amila Akagic and
Emir Buza and
Razija Turcinhodzic and
Hana Haseljic and
Hiroyuki Noda and
Hideharu Amano},
title = {Superpixel Accelerator for Computer Vision Applications on Arria 10
SoC},
booktitle = {21st {IEEE} International Symposium on Design and Diagnostics of Electronic
Circuits {\&} Systems, {DDECS} 2018, Budapest, Hungary, April
25-27, 2018},
pages = {55--60},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/DDECS.2018.00-12},
doi = {10.1109/DDECS.2018.00-12},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ddecs/AkagicBTHNA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/YasudoVCLA18,
author = {Ryota Yasudo and
Ana Lucia Varbanescu and
Jos{\'{e}} Gabriel F. Coutinho and
Wayne Luk and
Hideharu Amano},
title = {Performance Prediction for Large-Scale Heterogeneous Platforms},
booktitle = {26th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2018, Boulder, CO, USA, April 29 - May
1, 2018},
pages = {220},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/FCCM.2018.00054},
doi = {10.1109/FCCM.2018.00054},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/YasudoVCLA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KojimaA18,
author = {Takuya Kojima and
Hideharu Amano},
title = {A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable
Architectures},
booktitle = {28th International Conference on Field Programmable Logic and Applications,
{FPL} 2018, Dublin, Ireland, August 27-31, 2018},
pages = {239--242},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/FPL.2018.00048},
doi = {10.1109/FPL.2018.00048},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/KojimaA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/Amano18,
author = {Hideharu Amano},
title = {Accelerator-in-Switch: {A} Novel Cooperation Framework for FPGAs and
GPUs},
booktitle = {International Conference on Field-Programmable Technology, {FPT} 2018,
Naha, Okinawa, Japan, December 10-14, 2018},
pages = {22},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/FPT.2018.00010},
doi = {10.1109/FPT.2018.00010},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/Amano18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/YasudoCVLAB18,
author = {Ryota Yasudo and
Jos{\'{e}} Gabriel F. Coutinho and
Ana Lucia Varbanescu and
Wayne Luk and
Hideharu Amano and
Tobias Becker},
title = {Performance Estimation for Exascale Reconfigurable Dataflow Platforms},
booktitle = {International Conference on Field-Programmable Technology, {FPT} 2018,
Naha, Okinawa, Japan, December 10-14, 2018},
pages = {314--317},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/FPT.2018.00062},
doi = {10.1109/FPT.2018.00062},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/YasudoCVLAB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/WeiHA18,
author = {Kaijie Wei and
Koki Honda and
Hideharu Amano},
title = {{FPGA} Design for Autonomous Vehicle Driving Using Binarized Neural
Networks},
booktitle = {International Conference on Field-Programmable Technology, {FPT} 2018,
Naha, Okinawa, Japan, December 10-14, 2018},
pages = {425--428},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/FPT.2018.00091},
doi = {10.1109/FPT.2018.00091},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/WeiHA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/KojimaAMODA18,
author = {Takuya Kojima and
Naoki Ando and
Yusuke Matshushita and
Hayate Okuhara and
Ng. Anh Vu Doan and
Hideharu Amano},
title = {Real Chip Evaluation of a Low Power {CGRA} with Optimized Application
Mapping},
booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
ON, Canada, June 20-22, 2018},
pages = {13:1--13:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3241793.3241806},
doi = {10.1145/3241793.3241806},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/heart/KojimaAMODA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/KawanoYMA18,
author = {Ryuta Kawano and
Ryota Yasudo and
Hiroki Matsutani and
Hideharu Amano},
title = {k-Optimized Path Routing for High-Throughput Data Center Networks},
booktitle = {Sixth International Symposium on Computing and Networking, {CANDAR}
2018, Takayama, Japan, November 23-27, 2018},
pages = {99--105},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/CANDAR.2018.00020},
doi = {10.1109/CANDAR.2018.00020},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/KawanoYMA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/NiwaTMKA18,
author = {Naoya Niwa and
Tomohiro Totoki and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {An Trace-Driven Performance Prediction Method for Exploring NoC Design
Optimization},
booktitle = {Sixth International Symposium on Computing and Networking, {CANDAR}
Workshops 2018, Takayama, Japan, November 27-30, 2018},
pages = {182--185},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/CANDARW.2018.00042},
doi = {10.1109/CANDARW.2018.00042},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ic-nc/NiwaTMKA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/ShimuraNA18,
author = {Hideki Shimura and
Hiroyuki Noda and
Hideharu Amano},
title = {{C4:} An FPGA-based Compression Algorithm for ExpEther},
booktitle = {Sixth International Symposium on Computing and Networking, {CANDAR}
Workshops 2018, Takayama, Japan, November 27-30, 2018},
pages = {356--362},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/CANDARW.2018.00072},
doi = {10.1109/CANDARW.2018.00072},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/ShimuraNA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/TotokiKA18,
author = {Tomohiro Totoki and
Michihiro Koibuchi and
Hideharu Amano},
title = {An Extension of {A} Temperature Modeling Tool HotSpot 6.0 for Castle-of-Chips
Stacking},
booktitle = {Sixth International Symposium on Computing and Networking, {CANDAR}
Workshops 2018, Takayama, Japan, November 27-30, 2018},
pages = {363--369},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/CANDARW.2018.00073},
doi = {10.1109/CANDARW.2018.00073},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/TotokiKA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/AhmedOMKA18,
author = {Akram Ben Ahmed and
Hayate Okuhara and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip
Systems},
booktitle = {12th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2018, Hanoi, Vietnam, September 12-14, 2018},
pages = {146--153},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/MCSoC2018.2018.00034},
doi = {10.1109/MCSOC2018.2018.00034},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/AhmedOMKA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/AhmedFMKA18,
author = {Akram Ben Ahmed and
Daichi Fujiki and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
editor = {Zhonghai Lu and
Sriram R. Vangal and
Jiang Xu and
Paul Bogdan},
title = {AxNoC: Low-power Approximate Network-on-Chips using Critical-Path
Isolation},
booktitle = {Twelfth {IEEE/ACM} International Symposium on Networks-on-Chip, {NOCS}
2018, Torino, Italy, October 4-5, 2018},
pages = {6:1--6:8},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/NOCS.2018.8512158},
doi = {10.1109/NOCS.2018.8512158},
timestamp = {Wed, 05 May 2021 09:09:43 +0200},
biburl = {https://dblp.org/rec/conf/nocs/AhmedFMKA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nvmsa/UsamiAAKAIHSY18,
author = {Kimiyoshi Usami and
Junya Akaike and
Sosuke Akiba and
Masaru Kudo and
Hideharu Amano and
Takeharu Ikezoe and
Keizo Hiraga and
Yusuke Shuto and
Kojiro Yagami},
title = {Energy Efficient Write Verify and Retry Scheme for {MTJ} Based Flip-Flop
and Application},
booktitle = {{IEEE} 7th Non-Volatile Memory Systems and Applications Symposium,
{NVMSA} 2018, Hakodate, Sapporo, Japan, August 28-31, 2018},
pages = {91--98},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/NVMSA.2018.00023},
doi = {10.1109/NVMSA.2018.00023},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/nvmsa/UsamiAAKAIHSY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/IkezoeAAUKHSY18,
author = {Takeharu Ikezoe and
Hideharu Amano and
Junya Akaike and
Kimiyoshi Usami and
Masaru Kudo and
Keizo Hiraga and
Yusuke Shuto and
Kojiro Yagami},
editor = {David Andrews and
Ren{\'{e}} Cumplido and
Claudia Feregrino and
Dirk Stroobandt},
title = {A Coarse Grained-Reconfigurable Accelerator with energy efficient
MTJ-based Non-volatile Flip-flops},
booktitle = {2018 International Conference on ReConFigurable Computing and FPGAs,
ReConFig 2018, Cancun, Mexico, December 3-5, 2018},
pages = {1--6},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/RECONFIG.2018.8641712},
doi = {10.1109/RECONFIG.2018.8641712},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/IkezoeAAUKHSY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/sp/A2018,
editor = {Hideharu Amano},
title = {Principles and Structures of FPGAs},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-981-13-0824-6},
doi = {10.1007/978-981-13-0824-6},
isbn = {978-981-13-0823-9},
timestamp = {Tue, 11 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/sp/A2018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KawanoNTFMKA17,
author = {Ryuta Kawano and
Hiroshi Nakahara and
Seiichi Tade and
Ikki Fujiwara and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic
Routing},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {100-D},
number = {8},
pages = {1798--1806},
year = {2017},
url = {https://doi.org/10.1587/transinf.2016EDP7477},
doi = {10.1587/TRANSINF.2016EDP7477},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KawanoNTFMKA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KawanoNFMKA17,
author = {Ryuta Kawano and
Hiroshi Nakahara and
Ikki Fujiwara and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {A Layout-Oriented Routing Method for Low-Latency {HPC} Networks},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {100-D},
number = {12},
pages = {2796--2807},
year = {2017},
url = {https://doi.org/10.1587/transinf.2017PAP0019},
doi = {10.1587/TRANSINF.2017PAP0019},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KawanoNFMKA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/MatsushitaOMFKA17,
author = {Yusuke Matsushita and
Hayate Okuhara and
Koichiro Masuyama and
Yu Fujita and
Ryuta Kawano and
Hideharu Amano},
title = {Body Bias Domain Partitioning Size Exploration for a Coarse Grained
Reconfigurable Accelerator},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {100-D},
number = {12},
pages = {2828--2836},
year = {2017},
url = {https://doi.org/10.1587/transinf.2017PAP0013},
doi = {10.1587/TRANSINF.2017PAP0013},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/MatsushitaOMFKA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/YasudoMKAN17,
author = {Ryota Yasudo and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano and
Tadao Nakamura},
title = {Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized
Routers},
journal = {{IEEE} Trans. Computers},
volume = {66},
number = {4},
pages = {702--716},
year = {2017},
url = {https://doi.org/10.1109/TC.2016.2606597},
doi = {10.1109/TC.2016.2606597},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/YasudoMKAN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LeongAABCDGHLLL17,
author = {Philip Heng Wai Leong and
Hideharu Amano and
Jason Helge Anderson and
Koen Bertels and
Jo{\~{a}}o M. P. Cardoso and
Oliver Diessel and
Guy Gogniat and
Mike Hutton and
JunKyu Lee and
Wayne Luk and
Patrick Lysaght and
Marco Platzner and
Viktor K. Prasanna and
Tero Rissa and
Cristina Silvano and
Hayden Kwok{-}Hay So and
Yu Wang},
title = {The First 25 Years of the {FPL} Conference: Significant Papers},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {2},
pages = {15:1--15:17},
year = {2017},
url = {https://doi.org/10.1145/2996468},
doi = {10.1145/2996468},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LeongAABCDGHLLL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OkuharaFUA17,
author = {Hayate Okuhara and
Yu Fujita and
Kimiyoshi Usami and
Hideharu Amano},
title = {Power Optimization Methodology for Ultralow Power Microcontroller
With Silicon on Thin {BOX} {MOSFET}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1578--1582},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2635675},
doi = {10.1109/TVLSI.2016.2635675},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OkuharaFUA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cluster/KoibuchiTMACFC17,
author = {Michihiro Koibuchi and
Tomohiro Totoki and
Hiroki Matsutani and
Hideharu Amano and
Fabien Chaix and
Ikki Fujiwara and
Henri Casanova},
title = {A Case for Uni-directional Network Topologies in Large-Scale Clusters},
booktitle = {2017 {IEEE} International Conference on Cluster Computing, {CLUSTER}
2017, Honolulu, HI, USA, September 5-8, 2017},
pages = {178--187},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/CLUSTER.2017.33},
doi = {10.1109/CLUSTER.2017.33},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cluster/KoibuchiTMACFC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/AmanoNKKHBB17,
author = {Hideharu Amano and
Tadao Nakamura and
Hiroaki Kobayashi and
Hironori Kasahara and
Yoshiaki Hagiwara and
Jeffrey L. Burns and
David Brash},
title = {Panel discussions: "Cool chips for the next decade"},
booktitle = {2017 {IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} Chips
2017, Yokohama, Japan, April 19-21, 2017},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/CoolChips.2017.7946378},
doi = {10.1109/COOLCHIPS.2017.7946378},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/AmanoNKKHBB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/AzegamiOA17,
author = {Keita Azegami and
Hayate Okuhara and
Hideharu Amano},
title = {Body bias control for renewable energy source with a high inner resistance},
booktitle = {2017 {IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} Chips
2017, Yokohama, Japan, April 19-21, 2017},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/CoolChips.2017.7946386},
doi = {10.1109/COOLCHIPS.2017.7946386},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/AzegamiOA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/OkuharaAKA17,
author = {Hayate Okuhara and
Akram Ben Ahmed and
Johannes Maximilian K{\"{u}}hn and
Hideharu Amano},
title = {Leveraging asymmetric body bias control for low power {LSI} design},
booktitle = {2017 {IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} Chips
2017, Yokohama, Japan, April 19-21, 2017},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/CoolChips.2017.7946379},
doi = {10.1109/COOLCHIPS.2017.7946379},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/OkuharaAKA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KojimaAODA17,
author = {Takuya Kojima and
Naoki Ando and
Hayate Okuhara and
Ng. Anh Vu Doan and
Hideharu Amano},
editor = {Marco D. Santambrogio and
Diana G{\"{o}}hringer and
Dirk Stroobandt and
Nele Mentens and
Jari Nurmi},
title = {Body bias optimization for variable pipelined {CGRA}},
booktitle = {27th International Conference on Field Programmable Logic and Applications,
{FPL} 2017, Ghent, Belgium, September 4-8, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/FPL.2017.8056851},
doi = {10.23919/FPL.2017.8056851},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/KojimaAODA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/MitsuzukaHKAM17,
author = {Koya Mitsuzuka and
Ami Hayashi and
Michihiro Koibuchi and
Hideharu Amano and
Hiroki Matsutani},
editor = {Marco D. Santambrogio and
Diana G{\"{o}}hringer and
Dirk Stroobandt and
Nele Mentens and
Jari Nurmi},
title = {In-switch approximate processing: Delayed tasks management for MapReduce
applications},
booktitle = {27th International Conference on Field Programmable Logic and Applications,
{FPL} 2017, Ghent, Belgium, September 4-8, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/FPL.2017.8056802},
doi = {10.23919/FPL.2017.8056802},
timestamp = {Wed, 11 Oct 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/MitsuzukaHKAM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/TsurutaKNA17,
author = {Chiharu Tsuruta and
Takahiro Kaneda and
Naoki Nishikawa and
Hideharu Amano},
editor = {Marco D. Santambrogio and
Diana G{\"{o}}hringer and
Dirk Stroobandt and
Nele Mentens and
Jari Nurmi},
title = {Accelerator-in-switch: {A} framework for tightly coupled switching
hub and an accelerator with {FPGA}},
booktitle = {27th International Conference on Field Programmable Logic and Applications,
{FPL} 2017, Ghent, Belgium, September 4-8, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/FPL.2017.8056846},
doi = {10.23919/FPL.2017.8056846},
timestamp = {Wed, 11 Oct 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/TsurutaKNA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/SitKA17,
author = {Mankit Sit and
Ryosuke Kazami and
Hideharu Amano},
title = {FPGA-based accelerator for losslessly quantized convolutional neural
networks},
booktitle = {International Conference on Field Programmable Technology, {FPT} 2017,
Melbourne, Australia, December 11-13, 2017},
pages = {295--298},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/FPT.2017.8280164},
doi = {10.1109/FPT.2017.8280164},
timestamp = {Mon, 17 Feb 2020 13:32:07 +0100},
biburl = {https://dblp.org/rec/conf/fpt/SitKA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/KanedaSNHTA17,
author = {Takahiro Kaneda and
Ryotaro Sakai and
Naoki Nishikawa and
Toshihiro Hanawa and
Chiharu Tsuruta and
Hideharu Amano},
editor = {Diana G{\"{o}}hringer and
Michael H{\"{u}}bner},
title = {Performance Evaluation of {PEACH3:} Field-Programmable Gate Array
Switch for Tightly Coupled Accelerators},
booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
Germany, June 7-9, 2017},
pages = {9:1--9:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3120895.3120911},
doi = {10.1145/3120895.3120911},
timestamp = {Wed, 28 Apr 2021 16:06:55 +0200},
biburl = {https://dblp.org/rec/conf/heart/KanedaSNHTA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/NodaSMFA17,
author = {Hiroyuki Noda and
Ryotaro Sakai and
Takaaki Miyajima and
Naoyuki Fujita and
Hideharu Amano},
editor = {Diana G{\"{o}}hringer and
Michael H{\"{u}}bner},
title = {Acceleration of the aggregation process in a Hall-thruster simulation
using Intel {FPGA} {SDK} for OpenCL},
booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
Germany, June 7-9, 2017},
pages = {20:1--20:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3120895.3120915},
doi = {10.1145/3120895.3120915},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/heart/NodaSMFA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/FujikiIFMACK17,
author = {Daichi Fujiki and
Kiyo Ishii and
Ikki Fujiwara and
Hiroki Matsutani and
Hideharu Amano and
Henri Casanova and
Michihiro Koibuchi},
title = {High-Bandwidth Low-Latency Approximate Interconnection Networks},
booktitle = {2017 {IEEE} International Symposium on High Performance Computer Architecture,
{HPCA} 2017, Austin, TX, USA, February 4-8, 2017},
pages = {469--480},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/HPCA.2017.38},
doi = {10.1109/HPCA.2017.38},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hpca/FujikiIFMACK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/NomuraKKA17,
author = {Akio Nomura and
Junichiro Kadomoto and
Tadahiro Kuroda and
Hideharu Amano},
title = {A Practical Collision Avoidance Method for an Inter-Chip Bus with
Wireless Inductive through Chip Interface},
booktitle = {Fifth International Symposium on Computing and Networking, {CANDAR}
2017, Aomori, Japan, November 19-22, 2017},
pages = {126--131},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/CANDAR.2017.15},
doi = {10.1109/CANDAR.2017.15},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/NomuraKKA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccbdc/HuHFMAK17,
author = {Yao Hu and
Hiroaki Hara and
Ikki Fujiwara and
Hiroki Matsutani and
Hideharu Amano and
Michihiro Koibuchi},
title = {Towards Tightly-coupled Datacenter with Free-space Optical Links},
booktitle = {Proceedings of the 2017 International Conference on Cloud and Big
Data Computing, {ICCBDC} 2017, London, United Kingdom, September 17
- 19, 2017},
pages = {33--39},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3141128.3141130},
doi = {10.1145/3141128.3141130},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccbdc/HuHFMAK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpads/KawanoYMKA17,
author = {Ryuta Kawano and
Ryota Yasudo and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing
for Arbitrary Topologies},
booktitle = {23rd {IEEE} International Conference on Parallel and Distributed Systems,
{ICPADS} 2017, Shenzhen, China, December 15-17, 2017},
pages = {664--673},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ICPADS.2017.00091},
doi = {10.1109/ICPADS.2017.00091},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpads/KawanoYMKA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/YasudoKNMA17,
author = {Ryota Yasudo and
Michihiro Koibuchi and
Koji Nakano and
Hiroki Matsutani and
Hideharu Amano},
title = {Order/Radix Problem: Towards Low End-to-End Latency Interconnection
Networks},
booktitle = {46th International Conference on Parallel Processing, {ICPP} 2017,
Bristol, United Kingdom, August 14-17, 2017},
pages = {322--331},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ICPP.2017.41},
doi = {10.1109/ICPP.2017.41},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpp/YasudoKNMA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/YoshidaUA17,
author = {Yusuke Yoshida and
Kimiyoshi Usami and
Hideharu Amano},
title = {Digital embedded memory scheme using voltage scaling and body bias
separation for low-power system},
booktitle = {International SoC Design Conference, {ISOCC} 2017, Seoul, South Korea,
November 5-8, 2017},
pages = {148--149},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISOCC.2017.8368840},
doi = {10.1109/ISOCC.2017.8368840},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isocc/YoshidaUA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/KadomotoAK17,
author = {Junichiro Kadomoto and
Hideharu Amano and
Tadahiro Kuroda},
title = {An inductive-coupling link for 3-D Network-on-Chips},
booktitle = {International SoC Design Conference, {ISOCC} 2017, Seoul, South Korea,
November 5-8, 2017},
pages = {150--151},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISOCC.2017.8368841},
doi = {10.1109/ISOCC.2017.8368841},
timestamp = {Fri, 15 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isocc/KadomotoAK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/AmanoKNUKMN17,
author = {Hideharu Amano and
Tadahiro Kuroda and
Hiroshi Nakamura and
Kimiyoshi Usami and
Masaaki Kondo and
Hiroki Matsutani and
Mitaro Namiki},
title = {Building block multi-chip systems using inductive coupling through
chip interface},
booktitle = {International SoC Design Conference, {ISOCC} 2017, Seoul, South Korea,
November 5-8, 2017},
pages = {152--154},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISOCC.2017.8368842},
doi = {10.1109/ISOCC.2017.8368842},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isocc/AmanoKNUKMN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/SakamotoTIKNOKA17,
author = {Ryuichi Sakamoto and
Ryo Takata and
Jun Ishii and
Masaaki Kondo and
Hiroshi Nakamura and
Tetsui Ohkubo and
Takuya Kojima and
Hideharu Amano},
title = {Scalable deep neural network accelerator cores with cubic integration
using through chip interface},
booktitle = {International SoC Design Conference, {ISOCC} 2017, Seoul, South Korea,
November 5-8, 2017},
pages = {155--156},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISOCC.2017.8368843},
doi = {10.1109/ISOCC.2017.8368843},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isocc/SakamotoTIKNOKA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/HamadaKNA17,
author = {Shinsuke Hamada and
Atsushi Koshiba and
Mitaro Namiki and
Hideharu Amano},
title = {Building block operating system for 3D stacked computer systems with
inductive coupling interconnect},
booktitle = {International SoC Design Conference, {ISOCC} 2017, Seoul, South Korea,
November 5-8, 2017},
pages = {157--158},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISOCC.2017.8368844},
doi = {10.1109/ISOCC.2017.8368844},
timestamp = {Fri, 15 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isocc/HamadaKNA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispan/NakaharaYMAK17,
author = {Hiroshi Nakahara and
Ryota Yasudo and
Hiroki Matsutani and
Hideharu Amano and
Michihiro Koibuchi},
title = {3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip
Stack with Inductive Coupling Through Chip Interface},
booktitle = {14th International Symposium on Pervasive Systems, Algorithms and
Networks {\&} 11th International Conference on Frontier of Computer
Science and Technology {\&} Third International Symposium of Creative
Computing, {ISPAN-FCST-ISCC} 2017, Exeter, United Kingdom, June 21-23,
2017},
pages = {52--59},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ISPAN-FCST-ISCC.2017.82},
doi = {10.1109/ISPAN-FCST-ISCC.2017.82},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispan/NakaharaYMAK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/SakamotoTIKNOKA17,
author = {Ryuichi Sakamoto and
Ryo Takata and
Jun Ishii and
Masaaki Kondo and
Hiroshi Nakamura and
Tetsui Ohkubo and
Takuya Kojima and
Hideharu Amano},
title = {The Design and Implementation of Scalable Deep Neural Network Accelerator
Cores},
booktitle = {11th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2017, Seoul, South Korea, September 18-20,
2017},
pages = {13--20},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/MCSoC.2017.29},
doi = {10.1109/MCSOC.2017.29},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/SakamotoTIKNOKA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/DoanMAOA17,
author = {Nguyen Anh Vu Doan and
Yusuke Matsushita and
Naoki Ando and
Hayate Okuhara and
Hideharu Amano},
title = {Multi-objective Optimization for Application Mapping and Body Bias
Control on a {CGRA}},
booktitle = {11th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2017, Seoul, South Korea, September 18-20,
2017},
pages = {143--150},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/MCSoC.2017.20},
doi = {10.1109/MCSOC.2017.20},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/DoanMAOA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/NakaharaDYA17,
author = {Hiroshi Nakahara and
Ng. Anh Vu Doan and
Ryota Yasudo and
Hideharu Amano},
editor = {Axel Jantsch and
Hiroki Matsutani and
Zhonghai Lu and
{\"{U}}mit Y. Ogras},
title = {XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCs},
booktitle = {Proceedings of the Eleventh {IEEE/ACM} International Symposium on
Networks-on-Chip, {NOCS} 2017, Seoul, Republic of Korea, October 19
- 20, 2017},
pages = {17:1--17:8},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3130218.3130232},
doi = {10.1145/3130218.3130232},
timestamp = {Wed, 11 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nocs/NakaharaDYA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nss/NishikawaAI17,
author = {Naoki Nishikawa and
Hideharu Amano and
Keisuke Iwai},
editor = {Zheng Yan and
Refik Molva and
Wojciech Mazurczyk and
Raimo Kantola},
title = {Implementation of Bitsliced {AES} Encryption on CUDA-Enabled {GPU}},
booktitle = {Network and System Security - 11th International Conference, {NSS}
2017, Helsinki, Finland, August 21-23, 2017, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10394},
pages = {273--287},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-319-64701-2\_20},
doi = {10.1007/978-3-319-64701-2\_20},
timestamp = {Tue, 14 May 2019 10:00:41 +0200},
biburl = {https://dblp.org/rec/conf/nss/NishikawaAI17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/KojimaAOA17,
author = {Takuya Kojima and
Naoki Ando and
Hayate Okuhara and
Hideharu Amano},
title = {Glitch-aware variable pipeline optimization for CGRAs},
booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig
2017, Cancun, Mexico, December 4-6, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/RECONFIG.2017.8279797},
doi = {10.1109/RECONFIG.2017.8279797},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/KojimaAOA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/UsamiKYMA17,
author = {Kimiyoshi Usami and
Shunsuke Kogure and
Yusuke Yoshida and
Ryo Magasaki and
Hideharu Amano},
title = {Level-shifter-less approach for multi-VDD design to use body bias
control in {FD-SOI}},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203473},
doi = {10.1109/VLSI-SOC.2017.8203473},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/UsamiKYMA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/UsamiKYMA17a,
author = {Kimiyoshi Usami and
Shunsuke Kogure and
Yusuke Yoshida and
Ryo Magasaki and
Hideharu Amano},
editor = {Michail Maniatakos and
Ibrahim Abe M. Elfadel and
Matteo Sonza Reorda and
H. Fatih Ugurdag and
Jos{\'{e}} Monteiro and
Ricardo Reis},
title = {Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body
Bias Control in {FD-SOI}},
booktitle = {VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things
- 25th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates,
October 23-25, 2017, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {500},
pages = {1--21},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-030-15663-3\_1},
doi = {10.1007/978-3-030-15663-3\_1},
timestamp = {Tue, 12 Sep 2023 07:57:22 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/UsamiKYMA17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceee/KoibuchiFINCMAK16,
author = {Michihiro Koibuchi and
Ikki Fujiwara and
Kiyo Ishii and
Shu Namiki and
Fabien Chaix and
Hiroki Matsutani and
Hideharu Amano and
Tomohiro Kudoh},
title = {Optical network technologies for {HPC:} computer-architects point
of view},
journal = {{IEICE} Electron. Express},
volume = {13},
number = {6},
pages = {20152007},
year = {2016},
url = {https://doi.org/10.1587/elex.13.20152007},
doi = {10.1587/ELEX.13.20152007},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceee/KoibuchiFINCMAK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/AhmedMKUA16,
author = {Akram Ben Ahmed and
Hiroki Matsutani and
Michihiro Koibuchi and
Kimiyoshi Usami and
Hideharu Amano},
title = {Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency
for Low-Power Network-on-Chips Systems},
journal = {{IEICE} Trans. Electron.},
volume = {99-C},
number = {8},
pages = {909--917},
year = {2016},
url = {https://doi.org/10.1587/transele.E99.C.909},
doi = {10.1587/TRANSELE.E99.C.909},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/AhmedMKUA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KoshibaSUASKNN16,
author = {Atsushi Koshiba and
Mikiko Sato and
Kimiyoshi Usami and
Hideharu Amano and
Ryuichi Sakamoto and
Masaaki Kondo and
Hiroshi Nakamura and
Mitaro Namiki},
title = {An Operating System Guided Fine-Grained Power Gating Control Based
on Runtime Characteristics of Applications},
journal = {{IEICE} Trans. Electron.},
volume = {99-C},
number = {8},
pages = {926--935},
year = {2016},
url = {https://doi.org/10.1587/transele.E99.C.926},
doi = {10.1587/TRANSELE.E99.C.926},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/KoshibaSUASKNN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/NakaharaOMKA16,
author = {Hiroshi Nakahara and
Tomoya Ozaki and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {Novel Chip Stacking Methods to Extend Both Horizontally and Vertically
for Many-Core Architectures with ThrouChip Interface},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {99-D},
number = {12},
pages = {2871--2880},
year = {2016},
url = {https://doi.org/10.1587/transinf.2016PAP0033},
doi = {10.1587/TRANSINF.2016PAP0033},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/NakaharaOMKA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KagamiMKTKA16,
author = {Takahiro Kagami and
Hiroki Matsutani and
Michihiro Koibuchi and
Yasuhiro Take and
Tadahiro Kuroda and
Hideharu Amano},
title = {Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {2},
pages = {493--506},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2418216},
doi = {10.1109/TVLSI.2015.2418216},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KagamiMKTKA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ACISicis/KawanoNTFMKA16,
author = {Ryuta Kawano and
Hiroshi Nakahara and
Seiichi Tade and
Ikki Fujiwara and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {{ACRO:} Assignment of channels in reverse order to make arbitrary
routing deadlock-free},
booktitle = {15th {IEEE/ACIS} International Conference on Computer and Information
Science, {ICIS} 2016, Okayama, Japan, June 26-29, 2016},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ICIS.2016.7550818},
doi = {10.1109/ICIS.2016.7550818},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ACISicis/KawanoNTFMKA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/SugimotoMSOFA16,
author = {Naru Sugimoto and
Takaaki Miyajima and
Ryotaro Sakai and
Yasunori Osana and
Naoyuki Fujita and
Hideharu Amano},
editor = {Vanderlei Bonato and
Christos Bouganis and
Marek Gorgon},
title = {Zynq Cluster for {CFD} Parametric Survey},
booktitle = {Applied Reconfigurable Computing - 12th International Symposium, {ARC}
2016, Mangaratiba, RJ, Brazil, March 22-24, 2016, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {9625},
pages = {287--299},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-30481-6\_23},
doi = {10.1007/978-3-319-30481-6\_23},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arc/SugimotoMSOFA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/KadomotoMAK16,
author = {Junichiro Kadomoto and
Tomoki Miyata and
Hideharu Amano and
Tadahiro Kuroda},
title = {An inductive-coupling bus with collision detection scheme using magnetic
field variation for 3-D network-on-chips},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
Japan, November 7-9, 2016},
pages = {41--44},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASSCC.2016.7844130},
doi = {10.1109/ASSCC.2016.7844130},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/asscc/KadomotoMAK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cd/MatsuokaANIKMTI16,
author = {Satoshi Matsuoka and
Hideharu Amano and
Kengo Nakajima and
Koji Inoue and
Tomohiro Kudoh and
Naoya Maruyama and
Kenjiro Taura and
Takeshi Iwashita and
Takahiro Katagiri and
Toshihiro Hanawa and
Toshio Endo},
editor = {Gianluca Palermo and
John Feo},
title = {From {FLOPS} to {BYTES:} disruptive change in high-performance computing
towards the post-moore era},
booktitle = {Proceedings of the {ACM} International Conference on Computing Frontiers,
CF'16, Como, Italy, May 16-19, 2016},
pages = {274--281},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2903150.2906830},
doi = {10.1145/2903150.2906830},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cd/MatsuokaANIKMTI16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/KuhnAOABR16,
author = {Johannes Maximilian K{\"{u}}hn and
Akram Ben Ahmed and
Hayate Okuhara and
Hideharu Amano and
Oliver Bringmann and
Wolfgang Rosenstiel},
title = {MuCCRA4-BB: {A} fine-grained body biasing capable {DRP}},
booktitle = {2016 {IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
XIX, Yokohama, Japan, April 20-22, 2016},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/CoolChips.2016.7503676},
doi = {10.1109/COOLCHIPS.2016.7503676},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/KuhnAOABR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KuhnABR16,
author = {Johannes Maximilian K{\"{u}}hn and
Hideharu Amano and
Oliver Bringmann and
Wolfgang Rosenstiel},
title = {Leveraging {FDSOI} through body bias domain partitioning and bias
search},
booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
2016, Austin, TX, USA, June 5-9, 2016},
pages = {79:1--79:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2897937.2898039},
doi = {10.1145/2897937.2898039},
timestamp = {Fri, 29 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KuhnABR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/MatsushitaOMFKA16,
author = {Yusuke Matsushita and
Hayate Okuhara and
Koichiro Masuyama and
Yu Fujita and
Ryuta Kawano and
Hideharu Amano},
editor = {Paolo Ienne and
Walid A. Najjar and
Jason Helge Anderson and
Philip Brisk and
Walter Stechele},
title = {Body bias grain size exploration for a coarse grained reconfigurable
accelerator},
booktitle = {26th International Conference on Field Programmable Logic and Applications,
{FPL} 2016, Lausanne, Switzerland, August 29 - September 2, 2016},
pages = {1--4},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/FPL.2016.7577346},
doi = {10.1109/FPL.2016.7577346},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/MatsushitaOMFKA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/AndoMOA16,
author = {Naoki Ando and
Koichiro Masuyama and
Hayate Okuhara and
Hideharu Amano},
editor = {Yuchen Song and
Shaojun Wang and
Brent Nelson and
Junbao Li and
Yu Peng},
title = {Variable pipeline structure for Coarse Grained Reconfigurable Array
{CMA}},
booktitle = {2016 International Conference on Field-Programmable Technology, {FPT}
2016, Xi'an, China, December 7-9, 2016},
pages = {217--220},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/FPT.2016.7929537},
doi = {10.1109/FPT.2016.7929537},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/AndoMOA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/NakaharaOSSTKA16,
author = {Hiroshi Nakahara and
Tetsui Ohkubo and
Hideki Shimura and
Ryotaro Sakai and
Chiharu Tsuruta and
Takahiro Kaneda and
Hideharu Amano},
editor = {Yuchen Song and
Shaojun Wang and
Brent Nelson and
Junbao Li and
Yu Peng},
title = {Trax solver on Zynq using incremental update algorithm},
booktitle = {2016 International Conference on Field-Programmable Technology, {FPT}
2016, Xi'an, China, December 7-9, 2016},
pages = {323--326},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/FPT.2016.7929564},
doi = {10.1109/FPT.2016.7929564},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/NakaharaOSSTKA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/KawanoNFMKA16,
author = {Ryuta Kawano and
Hiroshi Nakahara and
Ikki Fujiwara and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {{LOREN:} {A} Scalable Routing Method for Layout-Conscious Random Topologies},
booktitle = {Fourth International Symposium on Computing and Networking, {CANDAR}
2016, Hiroshima, Japan, November 22-25, 2016},
pages = {9--18},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/CANDAR.2016.0019},
doi = {10.1109/CANDAR.2016.0019},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/KawanoNFMKA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/ShimuraMKYA16,
author = {Hideki Shimura and
Takuji Mitsuishi and
Masaki Kan and
Takashi Yoshikawa and
Hideharu Amano},
title = {On-the-Fly Data Compression/Decompression Mechanism with ExpEther},
booktitle = {Fourth International Symposium on Computing and Networking, {CANDAR}
2016, Hiroshima, Japan, November 22-25, 2016},
pages = {112--118},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/CANDAR.2016.0031},
doi = {10.1109/CANDAR.2016.0031},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/ShimuraMKYA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/NomuraMKKMA16,
author = {Akio Nomura and
Hiroki Matsutani and
Tadahiro Kuroda and
Junichiro Kadomoto and
Yusuke Matsushita and
Hideharu Amano},
title = {Vertical Packet Switching Elevator Network Using Inductive Coupling
ThruChip Interface},
booktitle = {Fourth International Symposium on Computing and Networking, {CANDAR}
2016, Hiroshima, Japan, November 22-25, 2016},
pages = {195--201},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/CANDAR.2016.0043},
doi = {10.1109/CANDAR.2016.0043},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/NomuraMKKMA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/MitsuishiKTA16,
author = {Takuji Mitsuishi and
Takahiro Kaneda and
Sunao Torii and
Hideharu Amano},
title = {Implementing Breadth-First Search on a Compact Supercomputer Suiren},
booktitle = {Fourth International Symposium on Computing and Networking, {CANDAR}
2016, Hiroshima, Japan, November 22-25, 2016},
pages = {395--401},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/CANDAR.2016.0075},
doi = {10.1109/CANDAR.2016.0075},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/MitsuishiKTA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/SakaiSMFA16,
author = {Ryotaro Sakai and
Naru Sugimoto and
Takaaki Miyajima and
Naoyuki Fujita and
Hideharu Amano},
title = {Acceleration of Full-PIC Simulation on a {CPU-FPGA} Tightly Coupled
Environment},
booktitle = {10th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, {MCSOC} 2016, Lyon, France, September 21-23, 2016},
pages = {8--14},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/MCSoC.2016.33},
doi = {10.1109/MCSOC.2016.33},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/SakaiSMFA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdp/FujikiMKA16,
author = {Daichi Fujiki and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {Randomizing Packet Memory Networks for Low-Latency Processor-Memory
Communication},
booktitle = {24th Euromicro International Conference on Parallel, Distributed,
and Network-Based Processing, {PDP} 2016, Heraklion, Crete, Greece,
February 17-19, 2016},
pages = {168--175},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/PDP.2016.18},
doi = {10.1109/PDP.2016.18},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/pdp/FujikiMKA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/IshibashiSKUAKP15,
author = {Koichiro Ishibashi and
Nobuyuki Sugii and
Shiro Kamohara and
Kimiyoshi Usami and
Hideharu Amano and
Kazutoshi Kobayashi and
Cong{-}Kha Pham},
title = {A Perpetuum Mobile 32bit {CPU} on 65nm {SOTB} {CMOS} Technology with
Reverse-Body-Bias Assisted Sleep Mode},
journal = {{IEICE} Trans. Electron.},
volume = {98-C},
number = {7},
pages = {536--543},
year = {2015},
url = {https://doi.org/10.1587/transele.E98.C.536},
doi = {10.1587/TRANSELE.E98.C.536},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/IshibashiSKUAKP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KoshibaWSSKUAKN15,
author = {Atsushi Koshiba and
Motoki Wada and
Ryuichi Sakamoto and
Mikiko Sato and
Tsubasa Kosaka and
Kimiyoshi Usami and
Hideharu Amano and
Masaaki Kondo and
Hiroshi Nakamura and
Mitaro Namiki},
title = {A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption
of Processor Functional Units},
journal = {{IEICE} Trans. Electron.},
volume = {98-C},
number = {7},
pages = {559--568},
year = {2015},
url = {https://doi.org/10.1587/transele.E98.C.559},
doi = {10.1587/TRANSELE.E98.C.559},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/KoshibaWSSKUAKN15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijnc/IzawaOKUA15,
author = {Mai Izawa and
Nobuaki Ozaki and
Yusuke Koizumi and
Rie Uno and
Hideharu Amano},
title = {A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator
{CMA}},
journal = {Int. J. Netw. Comput.},
volume = {5},
number = {1},
pages = {239--251},
year = {2015},
url = {http://www.ijnc.org/index.php/ijnc/article/view/105},
timestamp = {Tue, 16 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijnc/IzawaOKUA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/MiyajimaTA15,
author = {Takaaki Miyajima and
David B. Thomas and
Hideharu Amano},
title = {Courier: {A} Toolchain for Application Acceleration on Heterogeneous
Platforms},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {105--115},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.105},
doi = {10.2197/IPSJTSLDM.8.105},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/MiyajimaTA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jip/MiyajimaTA15,
author = {Takaaki Miyajima and
David B. Thomas and
Hideharu Amano},
title = {A Toolchain for Dynamic Function Off-load on {CPU-FPGA} Platforms},
journal = {J. Inf. Process.},
volume = {23},
number = {2},
pages = {153--162},
year = {2015},
url = {https://doi.org/10.2197/ipsjjip.23.153},
doi = {10.2197/IPSJJIP.23.153},
timestamp = {Tue, 16 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jip/MiyajimaTA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TsurutaMKAU15,
author = {Chiharu Tsuruta and
Yohei Miki and
Takuya Kuhara and
Hideharu Amano and
Masayuki Umemura},
title = {Off-Loading {LET} Generation to {PEACH2:} {A} Switching Hub for High
Performance {GPU} Clusters},
journal = {{SIGARCH} Comput. Archit. News},
volume = {43},
number = {4},
pages = {3--8},
year = {2015},
url = {https://doi.org/10.1145/2927964.2927966},
doi = {10.1145/2927964.2927966},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigarch/TsurutaMKAU15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/MitsuishiSHKA15,
author = {Takuji Mitsuishi and
Jun Suzuki and
Yuki Hayashi and
Masaki Kan and
Hideharu Amano},
title = {Breadth First Search on Cost-efficient Multi-GPU Systems},
journal = {{SIGARCH} Comput. Archit. News},
volume = {43},
number = {4},
pages = {58--63},
year = {2015},
url = {https://doi.org/10.1145/2927964.2927975},
doi = {10.1145/2927964.2927975},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigarch/MitsuishiSHKA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/HanawaKBAMUS15,
author = {Toshihiro Hanawa and
Yuetsu Kodama and
Taisuke Boku and
Hideharu Amano and
Hitoshi Murai and
Masayuki Umemura and
Mitsuhisa Sato},
editor = {Kentaro Sano and
Dimitrios Soudris and
Michael H{\"{u}}bner and
Pedro C. Diniz},
title = {Towards Unification of Accelerated Computing and Interconnection For
Extreme-Scale Computing},
booktitle = {Applied Reconfigurable Computing - 11th International Symposium, {ARC}
2015, Bochum, Germany, April 13-17, 2015, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {9040},
pages = {463--474},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-16214-0\_43},
doi = {10.1007/978-3-319-16214-0\_43},
timestamp = {Wed, 28 Apr 2021 16:06:56 +0200},
biburl = {https://dblp.org/rec/conf/arc/HanawaKBAMUS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/TadeMAK15,
author = {Seiichi Tade and
Hiroki Matsutani and
Hideharu Amano and
Michihiro Koibuchi},
title = {A metamorphotic Network-on-Chip for various types of parallel applications},
booktitle = {26th {IEEE} International Conference on Application-specific Systems,
Architectures and Processors, {ASAP} 2015, Toronto, ON, Canada, July
27-29, 2015},
pages = {98--105},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ASAP.2015.7245715},
doi = {10.1109/ASAP.2015.7245715},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/TadeMAK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/KuhnABR15,
author = {Johannes Maximilian K{\"{u}}hn and
Hideharu Amano and
Oliver Bringmann and
Wolfgang Rosenstiel},
title = {Fined-grained body biasing for frequency scaling in advanced {SOI}
processes},
booktitle = {2015 {IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
XVIII, Yokohama, Japan, April 13-15, 2015},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/CoolChips.2015.7158655},
doi = {10.1109/COOLCHIPS.2015.7158655},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/KuhnABR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/OkuharaUA15,
author = {Hayate Okuhara and
Kimiyoshi Usami and
Hideharu Amano},
title = {A leakage current monitor circuit using silicon on thin {BOX} {MOSFET}
for dynamic back gate bias control},
booktitle = {2015 {IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
XVIII, Yokohama, Japan, April 13-15, 2015},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/CoolChips.2015.7158656},
doi = {10.1109/COOLCHIPS.2015.7158656},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/OkuharaUA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KuhnPABR15,
author = {Johannes Maximilian K{\"{u}}hn and
Dustin Peterson and
Hideharu Amano and
Oliver Bringmann and
Wolfgang Rosenstiel},
editor = {Wolfgang Nebel and
David Atienza},
title = {Spatial and temporal granularity limits of body biasing in {UTBB-FDSOI}},
booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe
Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March
9-13, 2015},
pages = {876--879},
publisher = {{ACM}},
year = {2015},
url = {http://dl.acm.org/citation.cfm?id=2757015},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/KuhnPABR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KuharaTHA15,
author = {Takuya Kuhara and
Chiharu Tsuruta and
Toshihiro Hanawa and
Hideharu Amano},
title = {Reduction calculator in an {FPGA} based switching Hub for high performance
clusters},
booktitle = {25th International Conference on Field Programmable Logic and Applications,
{FPL} 2015, London, United Kingdom, September 2-4, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/FPL.2015.7293985},
doi = {10.1109/FPL.2015.7293985},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/KuharaTHA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/LeongAABCDGHLLL15,
author = {Philip Heng Wai Leong and
Hideharu Amano and
Jason Helge Anderson and
Koen Bertels and
Jo{\~{a}}o M. P. Cardoso and
Oliver Diessel and
Guy Gogniat and
Mike Hutton and
JunKyu Lee and
Wayne Luk and
Patrick Lysaght and
Marco Platzner and
Viktor K. Prasanna and
Tero Rissa and
Cristina Silvano and
Hayden Kwok{-}Hay So and
Yu Wang},
title = {Significant papers from the first 25 years of the {FPL} conference},
booktitle = {25th International Conference on Field Programmable Logic and Applications,
{FPL} 2015, London, United Kingdom, September 2-4, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/FPL.2015.7293747},
doi = {10.1109/FPL.2015.7293747},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/LeongAABCDGHLLL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/MasuyamaFOA15,
author = {Koichiro Masuyama and
Yu Fujita and
Hayate Okuhara and
Hideharu Amano},
title = {7MOPS/lemon-battery image processing demonstration with an ultra-low
power reconfigurable accelerator {CMA-SOTB-2}},
booktitle = {25th International Conference on Field Programmable Logic and Applications,
{FPL} 2015, London, United Kingdom, September 2-4, 2015},
pages = {1},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/FPL.2015.7293964},
doi = {10.1109/FPL.2015.7293964},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/MasuyamaFOA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/SugimotoMKTSSA15,
author = {Naru Sugimoto and
Takuji Mitsuishi and
Takahiro Kaneda and
Chiharu Tsuruta and
Ryotaro Sakai and
Hideki Shimura and
Hideharu Amano},
title = {Trax solver on Zynq with Deep Q-Network},
booktitle = {2015 International Conference on Field Programmable Technology, {FPT}
2015, Queenstown, New Zealand, December 7-9, 2015},
pages = {272--275},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/FPT.2015.7393122},
doi = {10.1109/FPT.2015.7393122},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/SugimotoMKTSSA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/FujitaOMA15,
author = {Yu Fujita and
Hayate Okuhara and
Koichiro Masuyama and
Hideharu Amano},
title = {Power Optimization Considering the Chip Temperature of Low Power Reconfigurable
Accelerator {CMA-SOTB}},
booktitle = {Third International Symposium on Computing and Networking, {CANDAR}
2015, Sapporo, Hokkaido, Japan, December 8-11, 2015},
pages = {21--29},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/CANDAR.2015.19},
doi = {10.1109/CANDAR.2015.19},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/FujitaOMA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/OkuharaKFUA15,
author = {Hayate Okuhara and
Kuniaki Kitamori and
Yu Fujita and
Kimiyoshi Usami and
Hideharu Amano},
title = {An optimal power supply and body bias voltage for a ultra low power
micro-controller with silicon on thin box {MOSFET}},
booktitle = {{IEEE/ACM} International Symposium on Low Power Electronics and Design,
{ISLPED} 2015, Rome, Italy, July 22-24, 2015},
pages = {207--212},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISLPED.2015.7273515},
doi = {10.1109/ISLPED.2015.7273515},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/islped/OkuharaKFUA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/NakaharaOMKA15,
author = {Hiroshi Nakahara and
Tomoya Ozaki and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {Expandable Chip Stacking Method for Many-core Architectures Consisting
of Tiny Chips},
booktitle = {{IEEE} 9th International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2015, Turin, Italy, September 23-25, 2015},
pages = {41--48},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/MCSoC.2015.26},
doi = {10.1109/MCSOC.2015.26},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/NakaharaOMKA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/NomuraFMA15,
author = {Akio Nomura and
Yu Fujita and
Hiroki Matsutani and
Hideharu Amano},
title = {3D Shared Bus Architecture Using Inductive Coupling Interconnect},
booktitle = {{IEEE} 9th International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2015, Turin, Italy, September 23-25, 2015},
pages = {259--266},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/MCSoC.2015.27},
doi = {10.1109/MCSOC.2015.27},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/NomuraFMA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/YasudoMKAN15,
author = {Ryota Yasudo and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano and
Tadao Nakamura},
editor = {Andr{\'{e}} Ivanov and
Diana Marculescu and
Partha Pratim Pande and
Jos{\'{e}} Flich and
Karthik Pattabiraman},
title = {On-Chip Decentralized Routers with Balanced Pipelines for Avoiding
Interconnect Bottleneck},
booktitle = {Proceedings of the 9th International Symposium on Networks-on-Chip,
{NOCS} 2015, Vancouver, BC, Canada, September 28-30, 2015},
pages = {16:1--16:8},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2786572.2786583},
doi = {10.1145/2786572.2786583},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nocs/YasudoMKAN15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdp/KawanoTFMAK15,
author = {Ryuta Kawano and
Seiichi Tade and
Ikki Fujiwara and
Hiroki Matsutani and
Hideharu Amano and
Michihiro Koibuchi},
editor = {Masoud Daneshtalab and
Marco Aldinucci and
Ville Lepp{\"{a}}nen and
Johan Lilius and
Mats Brorsson},
title = {Optimized Core-Links for Low-Latency NoCs},
booktitle = {23rd Euromicro International Conference on Parallel, Distributed,
and Network-Based Processing, {PDP} 2015, Turku, Finland, March 4-6,
2015},
pages = {172--176},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/PDP.2015.15},
doi = {10.1109/PDP.2015.15},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/pdp/KawanoTFMAK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/MasuyamaFOA15,
author = {Koichiro Masuyama and
Yu Fujita and
Hayate Okuhara and
Hideharu Amano},
editor = {Michael H{\"{u}}bner and
Maya B. Gokhale and
Ren{\'{e}} Cumplido},
title = {A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator
{CMA-SOTB-2}},
booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig
2015, Riviera Maya, Mexico, December 7-9, 2015},
pages = {1--6},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ReConFig.2015.7393280},
doi = {10.1109/RECONFIG.2015.7393280},
timestamp = {Wed, 28 Apr 2021 16:06:54 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/MasuyamaFOA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/AkamineTOFA14,
author = {Takayuki Akamine and
Mohamad Sofian Abu Talip and
Yasunori Osana and
Naoyuki Fujita and
Hideharu Amano},
title = {Reconfigurable Out-of-Order System for Fluid Dynamics Computation
Using Unstructured Mesh},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {97-D},
number = {5},
pages = {1225--1234},
year = {2014},
url = {https://doi.org/10.1587/transinf.E97.D.1225},
doi = {10.1587/TRANSINF.E97.D.1225},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/AkamineTOFA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ZhangMKA14,
author = {Hao Zhang and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {Dynamic Power Consumption Optimization for Inductive-Coupling based
Wireless 3D NoCs},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {7},
pages = {27--36},
year = {2014},
url = {https://doi.org/10.2197/ipsjtsldm.7.27},
doi = {10.2197/IPSJTSLDM.7.27},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ZhangMKA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/NomuraMSHKA14,
author = {Shimpei Nomura and
Takuji Mitsuishi and
Jun Suzuki and
Yuki Hayashi and
Masaki Kan and
Hideharu Amano},
title = {Performance Analysis of the Multi-GPU System with ExpEther},
journal = {{SIGARCH} Comput. Archit. News},
volume = {42},
number = {4},
pages = {9--14},
year = {2014},
url = {https://doi.org/10.1145/2693714.2693717},
doi = {10.1145/2693714.2693717},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigarch/NomuraMSHKA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/MitsuishiNSHKA14,
author = {Takuji Mitsuishi and
Shimpei Nomura and
Jun Suzuki and
Yuki Hayashi and
Masaki Kan and
Hideharu Amano},
title = {Accelerating Breadth First Search on {GPU-BOX}},
journal = {{SIGARCH} Comput. Archit. News},
volume = {42},
number = {4},
pages = {81--86},
year = {2014},
url = {https://doi.org/10.1145/2693714.2693729},
doi = {10.1145/2693714.2693729},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigarch/MitsuishiNSHKA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/TakeMSKKA14,
author = {Yasuhiro Take and
Hiroki Matsutani and
Daisuke Sasaki and
Michihiro Koibuchi and
Tadahiro Kuroda and
Hideharu Amano},
title = {3D NoC with Inductive-Coupling Links for Building-Block SiPs},
journal = {{IEEE} Trans. Computers},
volume = {63},
number = {3},
pages = {748--763},
year = {2014},
url = {https://doi.org/10.1109/TC.2012.249},
doi = {10.1109/TC.2012.249},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/TakeMSKKA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/UsamiKMKTWAKSNKN14,
author = {Kimiyoshi Usami and
Masaru Kudo and
Kensaku Matsunaga and
Tsubasa Kosaka and
Yoshihiro Tsurui and
Weihan Wang and
Hideharu Amano and
Hiroaki Kobayashi and
Ryuichi Sakamoto and
Mitaro Namiki and
Masaaki Kondo and
Hiroshi Nakamura},
title = {Design and control methodology for fine grain power gating based on
energy characterization and code profiling of microprocessors},
booktitle = {19th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2014, Singapore, January 20-23, 2014},
pages = {843--848},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASPDAC.2014.6742995},
doi = {10.1109/ASPDAC.2014.6742995},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/UsamiKMKTWAKSNKN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/IshibashiSUAKPM14,
author = {Koichiro Ishibashi and
Nobuyuki Sugii and
Kimiyoshi Usami and
Hideharu Amano and
Kazutoshi Kobayashi and
Cong{-}Kha Pham and
Hideki Makiyama and
Yoshiki Yamamoto and
Hirofumi Shinohara and
Toshiaki Iwamatsu and
Yasuo Yamaguchi and
Hidekazu Oda and
Takumi Hasegawa and
Shinobu Okanishi and
Hiroshi Yanagita and
Shiro Kamohara and
Masaru Kadoshima and
Keiichi Maekawa and
Tomohiro Yamashita and
Duc{-}Hung Le and
Takumu Yomogita and
Masaru Kudo and
Kuniaki Kitamori and
Shuya Kondo and
Yuuki Manzawa},
title = {A Perpetuum Mobile 32bit {CPU} with 13.4pJ/cycle, 0.14{\(\mathrm{\mu}\)}A
sleep current using Reverse Body Bias Assisted 65nm {SOTB} {CMOS}
technology},
booktitle = {2014 {IEEE} Symposium on Low-Power and High-Speed Chips, {COOL} Chips
XVII, Yokohama, Japan, April 14-16, 2014},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/CoolChips.2014.6842954},
doi = {10.1109/COOLCHIPS.2014.6842954},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/coolchips/IshibashiSUAKPM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/YasudoKANWOSN14,
author = {Ryota Yasudo and
Takahiro Kagami and
Hideharu Amano and
Yasunobu Nakase and
Masashi Watanabe and
Tsukasa Oishi and
Toru Shimizu and
Tadao Nakamura},
title = {A low power NoC router using the marching memory through type},
booktitle = {2014 {IEEE} Symposium on Low-Power and High-Speed Chips, {COOL} Chips
XVII, Yokohama, Japan, April 14-16, 2014},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/CoolChips.2014.6842960},
doi = {10.1109/COOLCHIPS.2014.6842960},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/YasudoKANWOSN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KondoKSWTNWAMKUKN14,
author = {Masaaki Kondo and
Hiroaki Kobayashi and
Ryuichi Sakamoto and
Motoki Wada and
Jun Tsukamoto and
Mitaro Namiki and
Weihan Wang and
Hideharu Amano and
Kensaku Matsunaga and
Masaru Kudo and
Kimiyoshi Usami and
Toshiya Komoda and
Hiroshi Nakamura},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Design and evaluation of fine-grained power-gating for embedded microprocessors},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--6},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.158},
doi = {10.7873/DATE.2014.158},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/KondoKSWTNWAMKUKN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MatsutaniKFKTKBMA14,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Ikki Fujiwara and
Takahiro Kagami and
Yasuhiro Take and
Tadahiro Kuroda and
Paul Bogdan and
Radu Marculescu and
Hideharu Amano},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Low-latency wireless 3D NoCs via randomized shortcut chips},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--6},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.286},
doi = {10.7873/DATE.2014.286},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/MatsutaniKFKTKBMA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KatagiriA14,
author = {Toru Katagiri and
Hideharu Amano},
title = {A high speed design and implementation of dynamically reconfigurable
processor using 28NM {SOI} technology},
booktitle = {24th International Conference on Field Programmable Logic and Applications,
{FPL} 2014, Munich, Germany, 2-4 September, 2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPL.2014.6927438},
doi = {10.1109/FPL.2014.6927438},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/KatagiriA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/SuFA14,
author = {Honlian Su and
Yu Fujita and
Hideharu Amano},
title = {Body bias control for a coarse grained reconfigurable accelerator
implemented with Silicon on Thin {BOX} technology},
booktitle = {24th International Conference on Field Programmable Logic and Applications,
{FPL} 2014, Munich, Germany, 2-4 September, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPL.2014.6927486},
doi = {10.1109/FPL.2014.6927486},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/SuFA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/FujitaMA14,
author = {Yu Fujita and
Koichiro Masuyama and
Hideharu Amano},
editor = {Jialin Chen and
Wenbo Yin and
Yuichiro Shibata and
Lingli Wang and
Hayden Kwok{-}Hay So and
Yuchun Ma},
title = {Image processing by {A} 0.3V 2MW coarse-grained reconfigurable accelerator
{CMA-SOTB} with a solar battery},
booktitle = {2014 International Conference on Field-Programmable Technology, {FPT}
2014, Shanghai, China, December 10-12, 2014},
pages = {354--357},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPT.2014.7082818},
doi = {10.1109/FPT.2014.7082818},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/FujitaMA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/SugimotoA14,
author = {Naru Sugimoto and
Hideharu Amano},
editor = {Jialin Chen and
Wenbo Yin and
Yuichiro Shibata and
Lingli Wang and
Hayden Kwok{-}Hay So and
Yuchun Ma},
title = {Hardware/software co-design architecture for Blokus Duo solver},
booktitle = {2014 International Conference on Field-Programmable Technology, {FPT}
2014, Shanghai, China, December 10-12, 2014},
pages = {358--361},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPT.2014.7082820},
doi = {10.1109/FPT.2014.7082820},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/SugimotoA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hotchips/KamoharaSIUAKP14,
author = {Shiro Kamohara and
Nobuyuki Sugii and
Koichiro Ishibashi and
Kimiyoshi Usami and
Hideharu Amano and
Kazutoshi Kobayashi and
Cong{-}Kha Pham},
title = {A perpetuum mobile 32bit {CPU} on 65nm {SOTB} {CMOS} technology with
reverse-body-bias assisted sleep mode},
booktitle = {2014 {IEEE} Hot Chips 26 Symposium (HCS), Cupertino, CA, USA, August
10-12, 2014},
pages = {1},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/HOTCHIPS.2014.7478838},
doi = {10.1109/HOTCHIPS.2014.7478838},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hotchips/KamoharaSIUAKP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/KuharaKHKBA14,
author = {Takuya Kuhara and
Takahiro Kaneda and
Toshihiro Hanawa and
Yuetsu Kodama and
Taisuke Boku and
Hideharu Amano},
title = {A Preliminarily Evaluation of {PEACH3:} {A} Switching Hub for Tightly
Coupled Accelerators},
booktitle = {Second International Symposium on Computing and Networking, {CANDAR}
2014, Shizuoka, Japan, December 10-12, 2014},
pages = {377--381},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/CANDAR.2014.44},
doi = {10.1109/CANDAR.2014.44},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/KuharaKHKBA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/MishraHKFOA14,
author = {Dipikarani Mishra and
Mao Hatto and
Takuya Kuhara and
Naoyuki Fujita and
Yasunori Osana and
Hideharu Amano},
title = {{FPGA} Implementation of Viscous Function in a Package for Computational
Fluid Dynamics},
booktitle = {Second International Symposium on Computing and Networking, {CANDAR}
2014, Shizuoka, Japan, December 10-12, 2014},
pages = {608--610},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/CANDAR.2014.33},
doi = {10.1109/CANDAR.2014.33},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ic-nc/MishraHKFOA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/issoc/UsamiMKTANKN14,
author = {Kimiyoshi Usami and
Makoto Miyauchi and
Masaru Kudo and
Kazumitsu Takagi and
Hideharu Amano and
Mitaro Namiki and
Masaaki Kondo and
Hiroshi Nakamura},
editor = {Jari Nurmi and
Peeter Ellervee and
Dragomir Milojevic and
Ondrej Daniel and
Tommi Paakki},
title = {Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain
power gating},
booktitle = {2014 International Symposium on System-on-Chip, SoC 2014, Tampere,
Finland, October 28-29, 2014},
pages = {1--7},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSOC.2014.6972438},
doi = {10.1109/ISSOC.2014.6972438},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/issoc/UsamiMKTANKN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/FujitaUA14,
author = {Yu Fujita and
Kimiyoshi Usami and
Hideharu Amano},
title = {A Thermal Management System for Building Block Computing Systems},
booktitle = {{IEEE} 8th International Symposium on Embedded Multicore/Manycore
SoCs, MCSoC 2014, Aizu-Wakamatsu, Japan, September 23-25, 2014},
pages = {165--171},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/MCSoC.2014.32},
doi = {10.1109/MCSOC.2014.32},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/FujitaUA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/YasudoKANWOSN14,
author = {Ryota Yasudo and
Takahiro Kagami and
Hideharu Amano and
Yasunobu Nakase and
Masashi Watanabe and
Tsukasa Oishi and
Toru Shimizu and
Tadao Nakamura},
editor = {Davide Bertozzi and
Luca Benini and
Sudhakar Yalamanchili and
J{\"{o}}rg Henkel},
title = {Design of a low power NoC router using Marching Memory Through type},
booktitle = {Eighth {IEEE/ACM} International Symposium on Networks-on-Chip, NoCS
2014, Ferrara, Italy, September 17-19, 2014},
pages = {111--118},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/NOCS.2014.7008769},
doi = {10.1109/NOCS.2014.7008769},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nocs/YasudoKANWOSN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/MiyajimaTA14,
author = {Takaaki Miyajima and
David B. Thomas and
Hideharu Amano},
title = {An Automatic Mixed Software Hardware Pipeline Builder for {CPU-FPGA}
Platforms},
journal = {CoRR},
volume = {abs/1408.4969},
year = {2014},
url = {http://arxiv.org/abs/1408.4969},
eprinttype = {arXiv},
eprint = {1408.4969},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/MiyajimaTA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/NakamuraWOUAKN13,
author = {Hiroshi Nakamura and
Weihan Wang and
Yuya Ohta and
Kimiyoshi Usami and
Hideharu Amano and
Masaaki Kondo and
Mitaro Namiki},
title = {Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit,
Architecture, and System Software Design},
journal = {{IEICE} Trans. Electron.},
volume = {96-C},
number = {4},
pages = {404--412},
year = {2013},
url = {https://doi.org/10.1587/transele.E96.C.404},
doi = {10.1587/TRANSELE.E96.C.404},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/NakamuraWOUAKN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/AkagicA13,
author = {Amila Akagic and
Hideharu Amano},
title = {High-Speed Fully-Adaptable {CRC} Accelerators},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {96-D},
number = {6},
pages = {1299--1308},
year = {2013},
url = {https://doi.org/10.1587/transinf.E96.D.1299},
doi = {10.1587/TRANSINF.E96.D.1299},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/AkagicA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/Amano13,
author = {Hideharu Amano},
title = {Foreword},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {96-D},
number = {8},
pages = {1581},
year = {2013},
url = {https://doi.org/10.1587/transinf.E96.D.1581},
doi = {10.1587/TRANSINF.E96.D.1581},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/Amano13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/Amano13a,
author = {Hideharu Amano},
title = {Foreword},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {96-D},
number = {12},
pages = {2513},
year = {2013},
url = {https://doi.org/10.1587/transinf.E96.D.2513},
doi = {10.1587/TRANSINF.E96.D.2513},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/Amano13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ZhangMTKA13,
author = {Hao Zhang and
Hiroki Matsutani and
Yasuhiro Take and
Tadahiro Kuroda and
Hideharu Amano},
title = {Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless
3-D NoCs},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {96-D},
number = {12},
pages = {2753--2764},
year = {2013},
url = {https://doi.org/10.1587/transinf.E96.D.2753},
doi = {10.1587/TRANSINF.E96.D.2753},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ZhangMTKA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijnc/TalipAHOFA13,
author = {Mohamad Sofian Abu Talip and
Takayuki Akamine and
Mao Hatto and
Yasunori Osana and
Naoyuki Fujita and
Hideharu Amano},
title = {Adaptive Flux Calculation Scheme in Advection Term Computation Using
Partial Reconfiguration},
journal = {Int. J. Netw. Comput.},
volume = {3},
number = {2},
pages = {289--306},
year = {2013},
url = {http://www.ijnc.org/index.php/ijnc/article/view/68},
timestamp = {Tue, 16 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijnc/TalipAHOFA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/AkagicA13,
author = {Amila Akagic and
Hideharu Amano},
title = {Design and Implementation of IP-based iSCSI Offload Engine on an {FPGA}},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {112--121},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.112},
doi = {10.2197/IPSJTSLDM.6.112},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/AkagicA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/MiuraKTMKASNUKN13,
author = {Noriyuki Miura and
Yusuke Koizumi and
Yasuhiro Take and
Hiroki Matsutani and
Tadahiro Kuroda and
Hideharu Amano and
Ryuichi Sakamoto and
Mitaro Namiki and
Kimiyoshi Usami and
Masaaki Kondo and
Hiroshi Nakamura},
title = {A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface},
journal = {{IEEE} Micro},
volume = {33},
number = {6},
pages = {6--15},
year = {2013},
url = {https://doi.org/10.1109/MM.2013.112},
doi = {10.1109/MM.2013.112},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/micro/MiuraKTMKASNUKN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aina/UnoOA13,
author = {Rie Uno and
Nobuaki Ozaki and
Hideharu Amano},
editor = {Leonard Barolli and
Fatos Xhafa and
Makoto Takizawa and
Tomoya Enokido and
Hui{-}Huang Hsu},
title = {Research of {PE} Array Connection Network for Cool Mega-Array},
booktitle = {27th International Conference on Advanced Information Networking and
Applications Workshops, {WAINA} 2013, Barcelona, Spain, March 25-28,
2013},
pages = {144--149},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/WAINA.2013.144},
doi = {10.1109/WAINA.2013.144},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aina/UnoOA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aina/HiraiwaA13,
author = {Jorge Hiraiwa and
Hideharu Amano},
editor = {Leonard Barolli and
Fatos Xhafa and
Makoto Takizawa and
Tomoya Enokido and
Hui{-}Huang Hsu},
title = {An {FPGA} Implementation of Reconfigurable Real-Time Vision Architecture},
booktitle = {27th International Conference on Advanced Information Networking and
Applications Workshops, {WAINA} 2013, Barcelona, Spain, March 25-28,
2013},
pages = {150--155},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/WAINA.2013.131},
doi = {10.1109/WAINA.2013.131},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aina/HiraiwaA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aina/DaikiMA13,
author = {Kugami Daiki and
Takaaki Miyajima and
Hideharu Amano},
editor = {Leonard Barolli and
Fatos Xhafa and
Makoto Takizawa and
Tomoya Enokido and
Hui{-}Huang Hsu},
title = {A Circuit Division Method for High-Level Synthesis on Multi-FPGA Systems},
booktitle = {27th International Conference on Advanced Information Networking and
Applications Workshops, {WAINA} 2013, Barcelona, Spain, March 25-28,
2013},
pages = {156--161},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/WAINA.2013.266},
doi = {10.1109/WAINA.2013.266},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aina/DaikiMA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/KuharaMYA13,
author = {Takuya Kuhara and
Takaaki Miyajima and
Masato Yoshimi and
Hideharu Amano},
editor = {Philip Brisk and
Jos{\'{e}} Gabriel F. Coutinho and
Pedro C. Diniz},
title = {An {FPGA} Acceleration for the Kd-tree Search in Photon Mapping},
booktitle = {Reconfigurable Computing: Architectures, Tools and Applications -
9th International Symposium, {ARC} 2013, Los Angeles, CA, USA, March
25-27, 2013. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7806},
pages = {25--36},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-642-36812-7\_3},
doi = {10.1007/978-3-642-36812-7\_3},
timestamp = {Fri, 27 Mar 2020 08:54:48 +0100},
biburl = {https://dblp.org/rec/conf/arc/KuharaMYA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/MatsutaniBMTSZKKA13,
author = {Hiroki Matsutani and
Paul Bogdan and
Radu Marculescu and
Yasuhiro Take and
Daisuke Sasaki and
Hao Zhang and
Michihiro Koibuchi and
Tadahiro Kuroda and
Hideharu Amano},
title = {A case for wireless 3D NoCs for CMPs},
booktitle = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2013, Yokohama, Japan, January 22-25, 2013},
pages = {23--28},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASPDAC.2013.6509553},
doi = {10.1109/ASPDAC.2013.6509553},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/MatsutaniBMTSZKKA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/0020MKA13,
author = {Hao Zhang and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {Dynamic power on/off method for 3D NoCs with wireless inductive-coupling
links},
booktitle = {2013 {IEEE} Symposium on Low-Power and High-Speed Chips, {COOL} Chips
XVI, Yokohama, Japan, April 17-19, 2013},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/CoolChips.2013.6547924},
doi = {10.1109/COOLCHIPS.2013.6547924},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/0020MKA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/MiuraKSTMKASNUK13,
author = {Noriyuki Miura and
Yusuke Koizumi and
Eiichi Sasaki and
Yasuhiro Take and
Hiroki Matsutani and
Tadahiro Kuroda and
Hideharu Amano and
Ryuichi Sakamoto and
Mitaro Namiki and
Kimiyoshi Usami and
Masaaki Kondo and
Hiroshi Nakamura},
title = {A scalable 3D heterogeneous multi-core processor with inductive-coupling
thruchip interface},
booktitle = {2013 {IEEE} Symposium on Low-Power and High-Speed Chips, {COOL} Chips
XVI, Yokohama, Japan, April 17-19, 2013},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/CoolChips.2013.6547916},
doi = {10.1109/COOLCHIPS.2013.6547916},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/MiuraKSTMKASNUK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KoizumiMTMKASNUKN13,
author = {Yusuke Koizumi and
Noriyuki Miura and
Yasuhiro Take and
Hiroki Matsutani and
Tadahiro Kuroda and
Hideharu Amano and
Ryuichi Sakamoto and
Mitaro Namiki and
Kimiyoshi Usami and
Masaaki Kondo and
Hiroshi Nakamura},
title = {Demonstration of a heterogeneous multi-core processor with 3-D inductive
coupling links},
booktitle = {23rd International Conference on Field programmable Logic and Applications,
{FPL} 2013, Porto, Portugal, September 2-4, 2013},
pages = {1},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPL.2013.6645628},
doi = {10.1109/FPL.2013.6645628},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/KoizumiMTMKASNUKN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ThomasA13,
author = {David B. Thomas and
Hideharu Amano},
title = {A fully pipelined {FPGA} architecture for stochastic simulation of
chemical systems},
booktitle = {23rd International Conference on Field programmable Logic and Applications,
{FPL} 2013, Porto, Portugal, September 2-4, 2013},
pages = {1--7},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPL.2013.6645506},
doi = {10.1109/FPL.2013.6645506},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/ThomasA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/TsusakaIUOA13,
author = {Akihito Tsusaka and
Mai Izawa and
Rie Uno and
Nobuyuki Ozaki and
Hideharu Amano},
title = {A hardware complete detection mechanism for an energy efficient reconfigurable
accelerator {CMA}},
booktitle = {23rd International Conference on Field programmable Logic and Applications,
{FPL} 2013, Porto, Portugal, September 2-4, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPL.2013.6645594},
doi = {10.1109/FPL.2013.6645594},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/TsusakaIUOA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/UnoOITMA13,
author = {Rie Uno and
Nobuaki Ozaki and
Mai Izawa and
Akihito Tsusaka and
Takaaki Miyajima and
Hideharu Amano},
title = {A speculative gather system for Cool Mega-Array},
booktitle = {2013 International Conference on Field-Programmable Technology, {FPT}
2013, Kyoto, Japan, December 9-11, 2013},
pages = {346--349},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPT.2013.6718383},
doi = {10.1109/FPT.2013.6718383},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/UnoOITMA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/TalipAHOFA13,
author = {Mohamad Sofian Abu Talip and
Takayuki Akamine and
Mao Hatto and
Yasunori Osana and
Naoyuki Fujita and
Hideharu Amano},
title = {Partially reconfigurable flux calculation scheme in advection term
computation},
booktitle = {2013 International Conference on Field-Programmable Technology, {FPT}
2013, Kyoto, Japan, December 9-11, 2013},
pages = {382--385},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPT.2013.6718393},
doi = {10.1109/FPT.2013.6718393},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/TalipAHOFA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/SuWKA13,
author = {Hongliang Su and
Weihan Wang and
Kuniaki Kitamori and
Hideharu Amano},
title = {A low power reconfigurable accelerator using a back-gate bias control
technique},
booktitle = {2013 International Conference on Field-Programmable Technology, {FPT}
2013, Kyoto, Japan, December 9-11, 2013},
pages = {390--393},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPT.2013.6718395},
doi = {10.1109/FPT.2013.6718395},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/SuWKA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/MiyajimaKHAB13,
author = {Takaaki Miyajima and
Takuya Kuhara and
Toshihiro Hanawa and
Hideharu Amano and
Taisuke Boku},
title = {Task level pipelining with {PEACH2:} An {FPGA} switching fabric for
high performance computing},
booktitle = {2013 International Conference on Field-Programmable Technology, {FPT}
2013, Kyoto, Japan, December 9-11, 2013},
pages = {466--469},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPT.2013.6718416},
doi = {10.1109/FPT.2013.6718416},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/MiyajimaKHAB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/SugimotoMKKMA13,
author = {Naru Sugimoto and
Takaaki Miyajima and
Takuya Kuhara and
Yuki Katuta and
Takushi Mitsuichi and
Hideharu Amano},
title = {Artificial intelligence of Blokus Duo on {FPGA} using Cyber Work Bench},
booktitle = {2013 International Conference on Field-Programmable Technology, {FPT}
2013, Kyoto, Japan, December 9-11, 2013},
pages = {498--501},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPT.2013.6718427},
doi = {10.1109/FPT.2013.6718427},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/SugimotoMKKMA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hotchips/MiuraKSTMKASNUK13,
author = {Noriyuki Miura and
Yusuke Koizumi and
Eiichi Sasaki and
Yasuhiro Take and
Hiroki Matsutani and
Tadahiro Kuroda and
Hideharu Amano and
Ryuichi Sakamoto and
Mitaro Namiki and
Kimiyoshi Usami and
Masaaki Kondo and
Hiroshi Nakamura},
title = {A scalable 3D heterogeneous multi-core processor with inductive-coupling
thruchip interface},
booktitle = {2013 {IEEE} Hot Chips 25 Symposium (HCS), Stanford University, CA,
USA, August 25-27, 2013},
pages = {1},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2013.7478328},
doi = {10.1109/HOTCHIPS.2013.7478328},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hotchips/MiuraKSTMKASNUK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/Amano13,
author = {Hideharu Amano},
editor = {Juan E. Guerrero},
title = {Tutorial: Introduction to Interconnection Networks from System Area
Network to Network on Chips},
booktitle = {The First International Symposium on Computing and Networking - Across
Practical Development and Theoretical Research, Dogo {SPA} Resort,
Matsuyama, Japan, December 4-6, 2013},
pages = {15--16},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/CANDAR.2013.9},
doi = {10.1109/CANDAR.2013.9},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/Amano13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/IzawaOKUA13,
author = {Mai Izawa and
Nobuyuki Ozaki and
Yusuke Koizumi and
Rie Uno and
Hideharu Amano},
editor = {Juan E. Guerrero},
title = {A Co-processor Design of an Energy Efficient Reconfigurable Accelerator
{CMA}},
booktitle = {The First International Symposium on Computing and Networking - Across
Practical Development and Theoretical Research, Dogo {SPA} Resort,
Matsuyama, Japan, December 4-6, 2013},
pages = {148--154},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/CANDAR.2013.28},
doi = {10.1109/CANDAR.2013.28},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/IzawaOKUA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ica3pp/SasakiZMKA13,
author = {Daisuke Sasaki and
Hao Zhang and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
editor = {Rocco Aversa and
Joanna Kolodziej and
Jun Zhang and
Flora Amato and
Giancarlo Fortino},
title = {A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs
by Maximizing Topological Regularity},
booktitle = {Algorithms and Architectures for Parallel Processing - 13th International
Conference, {ICA3PP} 2013, Vietri sul Mare, Italy, December 18-20,
2013, Proceedings, Part {II}},
series = {Lecture Notes in Computer Science},
volume = {8286},
pages = {77--85},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-319-03889-6\_9},
doi = {10.1007/978-3-319-03889-6\_9},
timestamp = {Tue, 14 May 2019 10:00:51 +0200},
biburl = {https://dblp.org/rec/conf/ica3pp/SasakiZMKA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/KagamiMKA13,
author = {Takahiro Kagami and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {Headfirst sliding routing: {A} time-based routing scheme for bus-NoC
hybrid 3-D architecture},
booktitle = {2013 Seventh {IEEE/ACM} International Symposium on Networks-on-Chip
(NoCS), Tempe, AZ, USA, April 21-24, 2013},
pages = {1--8},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/NoCS.2013.6558406},
doi = {10.1109/NOCS.2013.6558406},
timestamp = {Wed, 16 Oct 2019 14:14:48 +0200},
biburl = {https://dblp.org/rec/conf/nocs/KagamiMKA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/ChaintreuilUA13,
author = {Remi Chaintreuil and
Rie Uno and
Hideharu Amano},
title = {{MCMA:} {A} modular processing elements array based low-power coarse-grained
reconfigurable accelerator},
booktitle = {2012 International Conference on Reconfigurable Computing and FPGAs,
ReConFig 2013, Cancun, Mexico, December 9-11, 2013},
pages = {1--6},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ReConFig.2013.6732308},
doi = {10.1109/RECONFIG.2013.6732308},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/ChaintreuilUA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/Amano12,
author = {Hideharu Amano},
title = {Foreword},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {95-D},
number = {2},
pages = {293},
year = {2012},
url = {https://doi.org/10.1587/transinf.E95.D.293},
doi = {10.1587/TRANSINF.E95.D.293},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/Amano12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TalipAOFA12,
author = {Mohamad Sofian Abu Talip and
Takayuki Akamine and
Yasunori Osana and
Naoyuki Fujita and
Hideharu Amano},
title = {Partial Reconfiguration of Flux Limiter Functions in {MUSCL} Scheme
Using {FPGA}},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {95-D},
number = {10},
pages = {2369--2376},
year = {2012},
url = {https://doi.org/10.1587/transinf.E95.D.2369},
doi = {10.1587/TRANSINF.E95.D.2369},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/TalipAOFA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/Amano12a,
author = {Hideharu Amano},
title = {Foreword},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {95-D},
number = {12},
pages = {2749},
year = {2012},
url = {https://doi.org/10.1587/transinf.E95.D.2749},
doi = {10.1587/TRANSINF.E95.D.2749},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/Amano12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/TalipAOFA12,
author = {Mohamad Sofian Abu Talip and
Takayuki Akamine and
Yasunori Osana and
Naoyuki Fujita and
Hideharu Amano},
editor = {Oliver C. S. Choy and
Ray C. C. Cheung and
Peter M. Athanas and
Kentaro Sano},
title = {Cost Effective Implementation of Flux Limiter Functions Using Partial
Reconfiguration},
booktitle = {Reconfigurable Computing: Architectures, Tools and Applications -
8th International Symposium, {ARC} 2012, Hong Kong, China, March 19-23,
2012. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7199},
pages = {215--226},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-28365-9\_18},
doi = {10.1007/978-3-642-28365-9\_18},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arc/TalipAOFA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arcs/ZhangMTKA12,
author = {Hao Zhang and
Hiroki Matsutani and
Yasuhiro Take and
Tadahiro Kuroda and
Hideharu Amano},
editor = {Andreas Herkersdorf and
Kay R{\"{o}}mer and
Uwe Brinkschulte},
title = {Vertical Link On/Off Control Methods for Wireless 3-D NoCs},
booktitle = {Architecture of Computing Systems - {ARCS} 2012 - 25th International
Conference, Munich, Germany, February 28 - March 2, 2012. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7179},
pages = {212--224},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-28293-5\_18},
doi = {10.1007/978-3-642-28293-5\_18},
timestamp = {Thu, 14 Oct 2021 10:21:06 +0200},
biburl = {https://dblp.org/rec/conf/arcs/ZhangMTKA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/MatsutaniHKUNA12,
author = {Hiroki Matsutani and
Yuto Hirata and
Michihiro Koibuchi and
Kimiyoshi Usami and
Hiroshi Nakamura and
Hideharu Amano},
title = {A multi-Vdd dynamic variable-pipeline on-chip router for CMPs},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {407--412},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6164982},
doi = {10.1109/ASPDAC.2012.6164982},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/MatsutaniHKUNA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/WangOIUA12,
author = {Weihan Wang and
Yuya Ohta and
Yoshifumi Ishii and
Kimiyoshi Usami and
Hideharu Amano},
editor = {Hiroaki Kobayashi and
Makoto Ikeda and
Fumio Arakawa},
title = {Trade-off analysis of fine-grained power gating methods for functional
units in a {CPU}},
booktitle = {2012 {IEEE} Symposium on Low-Power and High-Speed Chips, {COOL} Chips
XV, Yokohama, Japan, April 18-20, 2012},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/COOLChips.2012.6216587},
doi = {10.1109/COOLCHIPS.2012.6216587},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/WangOIUA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/AkamineIOFA12,
author = {Takayuki Akamine and
Kenta Inakagata and
Yasunori Osana and
Naoyuki Fujita and
Hideharu Amano},
editor = {Dirk Koch and
Satnam Singh and
Jim T{\o}rresen},
title = {Reconfigurable out-of-order mechanism generator for unstructured grid
computation in computational fluid dynamics},
booktitle = {22nd International Conference on Field Programmable Logic and Applications
(FPL), Oslo, Norway, August 29-31, 2012},
pages = {136--142},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPL.2012.6339277},
doi = {10.1109/FPL.2012.6339277},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/AkamineIOFA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KoizumiSAMTKSNUKN12,
author = {Yusuke Koizumi and
Eiichi Sasaki and
Hideharu Amano and
Hiroki Matsutani and
Yasuhiro Take and
Tadahiro Kuroda and
Ryuichi Sakamoto and
Mitaro Namiki and
Kimiyoshi Usami and
Masaaki Kondo and
Hiroshi Nakamura},
editor = {Dirk Koch and
Satnam Singh and
Jim T{\o}rresen},
title = {CMA-Cube: {A} scalable reconfigurable accelerator with 3-D wireless
inductive coupling interconnect},
booktitle = {22nd International Conference on Field Programmable Logic and Applications
(FPL), Oslo, Norway, August 29-31, 2012},
pages = {543--546},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPL.2012.6339375},
doi = {10.1109/FPL.2012.6339375},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/KoizumiSAMTKSNUKN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/AkagicA12,
author = {Amila Akagic and
Hideharu Amano},
editor = {Dirk Koch and
Satnam Singh and
Jim T{\o}rresen},
title = {Performance analysis of fully-adaptable {CRC} accelerators on an {FPGA}},
booktitle = {22nd International Conference on Field Programmable Logic and Applications
(FPL), Oslo, Norway, August 29-31, 2012},
pages = {575--578},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPL.2012.6339374},
doi = {10.1109/FPL.2012.6339374},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/AkagicA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/AkagicA12,
author = {Amila Akagic and
Hideharu Amano},
title = {A study of adaptable co-processors for Cyclic Redundancy Check on
an {FPGA}},
booktitle = {2012 International Conference on Field-Programmable Technology, {FPT}
2012, Seoul, Korea (South), December 10-12, 2012},
pages = {119--124},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPT.2012.6412122},
doi = {10.1109/FPT.2012.6412122},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/AkagicA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/KoizumiAMMKSNUKN12,
author = {Yusuke Koizumi and
Hideharu Amano and
Hiroki Matsutani and
Noriyuki Miura and
Tadahiro Kuroda and
Ryuichi Sakamoto and
Mitaro Namiki and
Kimiyoshi Usami and
Masaaki Kondo and
Hiroshi Nakamura},
title = {Dynamic power control with a heterogeneous multi-core system using
a 3-D wireless inductive coupling interconnect},
booktitle = {2012 International Conference on Field-Programmable Technology, {FPT}
2012, Seoul, Korea (South), December 10-12, 2012},
pages = {293--296},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPT.2012.6412150},
doi = {10.1109/FPT.2012.6412150},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/KoizumiAMMKSNUKN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/MiyajimaTA12,
author = {Takaaki Miyajima and
David B. Thomas and
Hideharu Amano},
title = {A Domain Specific Language and Toolchain for OpenCV Runtime Binary
Acceleration Using {GPU}},
booktitle = {Third International Conference on Networking and Computing, {ICNC}
2012, Okinawa, Japan, December 5-7, 2012},
pages = {175--181},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ICNC.2012.34},
doi = {10.1109/ICNC.2012.34},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/MiyajimaTA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/KoibuchiMAHC12,
author = {Michihiro Koibuchi and
Hiroki Matsutani and
Hideharu Amano and
D. Frank Hsu and
Henri Casanova},
title = {A case for random shortcut topologies for {HPC} interconnects},
booktitle = {39th International Symposium on Computer Architecture {(ISCA} 2012),
June 9-13, 2012, Portland, OR, {USA}},
pages = {177--188},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ISCA.2012.6237016},
doi = {10.1109/ISCA.2012.6237016},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/KoibuchiMAHC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/NakamuraMKUA12,
author = {Takeo Nakamura and
Hiroki Matsutani and
Michihiro Koibuchi and
Kimiyoshi Usami and
Hideharu Amano},
title = {Fine-Grained Power Control Using {A} Multi-Voltage Variable Pipeline
Router},
booktitle = {{IEEE} 6th International Symposium on Embedded Multicore/Manycore
SoCs, MCSoC 2012, Fukushima, Japan, September 20-22, 2012},
pages = {59--66},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/MCSoC.2012.38},
doi = {10.1109/MCSOC.2012.38},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/NakamuraMKUA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/AmanoKO12,
author = {Hideharu Amano and
Masayuki Kimura and
Nobuaki Ozaki},
title = {Removing Context Memory from a Multi-context Dynamically Reconfigurable
Processor},
booktitle = {{IEEE} 6th International Symposium on Embedded Multicore/Manycore
SoCs, MCSoC 2012, Fukushima, Japan, September 20-22, 2012},
pages = {92--99},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/MCSoC.2012.35},
doi = {10.1109/MCSOC.2012.35},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/AmanoKO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nbis/Amano12,
author = {Hideharu Amano},
editor = {Leonard Barolli and
David Taniar and
Tomoya Enokido and
J. Wenny Rahayu and
Makoto Takizawa},
title = {Castle of Chips: {A} New Chip Stacking Structure with Wireless Inductive
Coupling for Large Scale 3-D Multicore Systems},
booktitle = {15th International Conference on Network-Based Information Systems,
NBiS 2012, Melbourne, Australia, September 26-28, 2012},
pages = {820--825},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/NBiS.2012.82},
doi = {10.1109/NBIS.2012.82},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nbis/Amano12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nbis/KatagiriHA12,
author = {Toru Katagiri and
Kazuei Hironaka and
Hideharu Amano},
editor = {Leonard Barolli and
David Taniar and
Tomoya Enokido and
J. Wenny Rahayu and
Makoto Takizawa},
title = {Extension of Memory Controller Equipped with MuCCRA-3-DP: Dynamically
Reconfigurable Processor Array},
booktitle = {15th International Conference on Network-Based Information Systems,
NBiS 2012, Melbourne, Australia, September 26-28, 2012},
pages = {826--831},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/NBiS.2012.87},
doi = {10.1109/NBIS.2012.87},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nbis/KatagiriHA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/recosoc/TalipAOFA12,
author = {Mohamad Sofian Abu Talip and
Takayuki Akamine and
Yasunori Osana and
Naoyuki Fujita and
Hideharu Amano},
editor = {Leandro Soares Indrusiak and
Guy Gogniat and
Nikolaos S. Voros},
title = {Dynamically reconfigurable flux limiter functions in {MUSCL} scheme},
booktitle = {7th International Workshop on Reconfigurable and Communication-Centric
Systems-on-Chip (ReCoSoC), York, United Kingdom, July 9-11, 2012},
pages = {1--7},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ReCoSoC.2012.6322878},
doi = {10.1109/RECOSOC.2012.6322878},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/recosoc/TalipAOFA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtcsa/SakamotoSKAN12,
author = {Ryuichi Sakamoto and
Mikiko Sato and
Yusuke Koizumi and
Hideharu Amano and
Mitaro Namiki},
title = {An OpenCL Runtime Library for Embedded Multi-Core Accelerator},
booktitle = {2012 {IEEE} International Conference on Embedded and Real-Time Computing
Systems and Applications, {RTCSA} 2012, Seoul, Korea (South), August
19-22, 2012},
pages = {419--422},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/RTCSA.2012.67},
doi = {10.1109/RTCSA.2012.67},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rtcsa/SakamotoSKAN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:reference/crc/SasakiAUKNN12,
author = {Hiroshi Sasaki and
Hideharu Amano and
Kimiyoshi Usami and
Masaaki Kondo and
Mitaro Namiki and
Hiroshi Nakamura},
editor = {Ishfaq Ahmad and
Sanjay Ranka},
title = {Geyser},
booktitle = {Handbook of Energy-Aware and Green Computing - Two Volume Set},
pages = {49--65},
publisher = {Chapman and Hall/CRC},
year = {2012},
url = {http://www.crcnetbase.com/doi/abs/10.1201/b16631-5},
doi = {10.1201/B16631-5},
timestamp = {Fri, 17 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/reference/crc/SasakiAUKNN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ZhaoXISNA11,
author = {Lei Zhao and
Hui Xu and
Daisuke Ikebuchi and
Tetsuya Sunata and
Mitaro Namiki and
Hideharu Amano},
title = {A Leakage Efficient Data {TLB} Design for Embedded Processors},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {94-D},
number = {1},
pages = {51--59},
year = {2011},
url = {https://doi.org/10.1587/transinf.E94.D.51},
doi = {10.1587/TRANSINF.E94.D.51},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ZhaoXISNA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/LeiXISNA11,
author = {Zhao Lei and
Hui Xu and
Daisuke Ikebuchi and
Tetsuya Sunata and
Mitaro Namiki and
Hideharu Amano},
title = {A Leakage Efficient Instruction {TLB} Design for Embedded Processors},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {94-D},
number = {8},
pages = {1565--1574},
year = {2011},
url = {https://doi.org/10.1587/transinf.E94.D.1565},
doi = {10.1587/TRANSINF.E94.D.1565},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/LeiXISNA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ToiOAWA11,
author = {Takao Toi and
Takumi Okamoto and
Toru Awashima and
Kazutoshi Wakabayashi and
Hideharu Amano},
title = {Iterative Synthesis Methods Estimating Programmable-Wire Congestion
in a Dynamically Reconfigurable Processor},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {94-A},
number = {12},
pages = {2619--2627},
year = {2011},
url = {https://doi.org/10.1587/transfun.E94.A.2619},
doi = {10.1587/TRANSFUN.E94.A.2619},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ToiOAWA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/LeiIUNKNA11,
author = {Zhao Lei and
Daisuke Ikebuchi and
Kimiyoshi Usami and
Mitaro Namiki and
Masaaki Kondo and
Hiroshi Nakamura and
Hideharu Amano},
title = {Design and Implementation Fine-grained Power Gating on Microprocessor
Functional Units},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {182--192},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.182},
doi = {10.2197/IPSJTSLDM.4.182},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/LeiIUNKNA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KaradumanSA11,
author = {Arda Karaduman and
Iver Stubdal and
Hideharu Amano},
title = {Design and Implementation of Echo Instructions for an Embedded Processor},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {222--231},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.222},
doi = {10.2197/IPSJTSLDM.4.222},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KaradumanSA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/NishikawaKYMA11,
author = {Yuri Nishikawa and
Michihiro Koibuchi and
Masato Yoshimi and
Kenichi Miura and
Hideharu Amano},
title = {An analytical network performance model for {SIMD} processor {CSX600}
interconnects},
journal = {J. Syst. Archit.},
volume = {57},
number = {1},
pages = {146--159},
year = {2011},
url = {https://doi.org/10.1016/j.sysarc.2010.10.004},
doi = {10.1016/J.SYSARC.2010.10.004},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/NishikawaKYMA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/OzakiYISIANUNK11,
author = {Nobuaki Ozaki and
Yoshihiro Yasuda and
Mai Izawa and
Yoshiki Saito and
Daisuke Ikebuchi and
Hideharu Amano and
Hiroshi Nakamura and
Kimiyoshi Usami and
Mitaro Namiki and
Masaaki Kondo},
title = {Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips},
journal = {{IEEE} Micro},
volume = {31},
number = {6},
pages = {6--18},
year = {2011},
url = {https://doi.org/10.1109/MM.2011.94},
doi = {10.1109/MM.2011.94},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/micro/OzakiYISIANUNK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/AkamineIOFA11,
author = {Takayuki Akamine and
Kenta Inakagata and
Yasunori Osana and
Naoyuki Fujita and
Hideharu Amano},
title = {An implementation of out-of-order execution system for acceleration
of computational fluid dynamics on FPGAs},
journal = {{SIGARCH} Comput. Archit. News},
volume = {39},
number = {4},
pages = {50--55},
year = {2011},
url = {https://doi.org/10.1145/2082156.2082169},
doi = {10.1145/2082156.2082169},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigarch/AkamineIOFA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/AkagicA11,
author = {Amila Akagic and
Hideharu Amano},
title = {High speed {CRC} with 64-bit generator polynomial on an {FPGA}},
journal = {{SIGARCH} Comput. Archit. News},
volume = {39},
number = {4},
pages = {72--77},
year = {2011},
url = {https://doi.org/10.1145/2082156.2082175},
doi = {10.1145/2082156.2082175},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigarch/AkagicA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/MatsutaniKAY11,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano and
Tsutomu Yoshinaga},
title = {Prediction Router: {A} Low-Latency On-Chip Router Architecture with
Multiple Predictors},
journal = {{IEEE} Trans. Computers},
volume = {60},
number = {6},
pages = {783--799},
year = {2011},
url = {https://doi.org/10.1109/TC.2011.17},
doi = {10.1109/TC.2011.17},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/MatsutaniKAY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MatsutaniKIUNA11,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Daisuke Ikebuchi and
Kimiyoshi Usami and
Hiroshi Nakamura and
Hideharu Amano},
title = {Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time
Power-Gating Routers for CMPs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {4},
pages = {520--533},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2110470},
doi = {10.1109/TCAD.2011.2110470},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MatsutaniKIUNA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/KoibuchiOKA11,
author = {Michihiro Koibuchi and
Tomohiro Otsuka and
Tomohiro Kudoh and
Hideharu Amano},
title = {A Switch-Tagged Routing Methodology for {PC} Clusters with {VLAN}
Ethernet},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {22},
number = {2},
pages = {217--230},
year = {2011},
url = {https://doi.org/10.1109/TPDS.2010.73},
doi = {10.1109/TPDS.2010.73},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/KoibuchiOKA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/YamamotoHHKAU11,
author = {Tatsuya Yamamoto and
Kazuei Hironaka and
Yuki Hayakawa and
Masayuki Kimura and
Hideharu Amano and
Kimiyoshi Usami},
editor = {Andreas Koch and
Ram Krishnamurthy and
John McAllister and
Roger F. Woods and
Tarek A. El{-}Ghazawi},
title = {Dynamic V\({}_{\mbox{DD}}\) Switching Technique and Mapping Optimization
in Dynamically Reconfigurable Processor for Efficient Energy Reduction},
booktitle = {Reconfigurable Computing: Architectures, Tools and Applications -
7th International Symposium, {ARC} 2011, Belfast, UK, March 23-25,
2011. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {6578},
pages = {230--241},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-19475-7\_24},
doi = {10.1007/978-3-642-19475-7\_24},
timestamp = {Fri, 25 Feb 2022 16:33:50 +0100},
biburl = {https://dblp.org/rec/conf/arc/YamamotoHHKAU11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ZhaoISKSKAKHUMUKNTNK11,
author = {Lei Zhao and
Daisuke Ikebuchi and
Yoshiki Saito and
M. Kamata and
Naomi Seki and
Yu Kojima and
Hideharu Amano and
Satoshi Koyama and
Tatsunori Hashida and
Y. Umahashi and
D. Masuda and
Kimiyoshi Usami and
Keiji Kimura and
Mitaro Namiki and
Seidai Takeda and
Hiroshi Nakamura and
Masaaki Kondo},
title = {Geyser-2: The second prototype {CPU} with fine-grained run-time power
gating},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {87--88},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722310},
doi = {10.1109/ASPDAC.2011.5722310},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ZhaoISKSKAKHUMUKNTNK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/OzakiUANNK11,
author = {Nobuaki Ozaki and
Kimiyoshi Usami and
Hideharu Amano and
Mitaro Namiki and
Hiroshi Nakamura and
Masaaki Kondo},
title = {SLD-1(Silent Large Datapath): {A} ultra low power reconfigurable accelerator},
booktitle = {2011 {IEEE} Symposium on Low-Power and High-Speed Chips, Cool Chips
XIV, Yokohama, Japan, 20-22 April, 2011},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/COOLCHIPS.2011.5890918},
doi = {10.1109/COOLCHIPS.2011.5890918},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/OzakiUANNK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/HironakaOA11,
author = {Kazuei Hironaka and
Nobuaki Ozaki and
Hideharu Amano},
editor = {Russell Tessier},
title = {The realtime image processing demonstration with {CMA-1:} An ultra
low-power reconfigurable accelerator},
booktitle = {2011 International Conference on Field-Programmable Technology, {FPT}
2011, New Delhi, India, December 12-14, 2011},
pages = {1--4},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/FPT.2011.6132686},
doi = {10.1109/FPT.2011.6132686},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/HironakaOA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/KimuraHA11,
author = {Masayuki Kimura and
Kazuei Hironaka and
Hideharu Amano},
editor = {Russell Tessier},
title = {Reducing power for dynamically reconfigurable processor array by reducing
number of reconfigurations},
booktitle = {2011 International Conference on Field-Programmable Technology, {FPT}
2011, New Delhi, India, December 12-14, 2011},
pages = {1--8},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/FPT.2011.6132707},
doi = {10.1109/FPT.2011.6132707},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/KimuraHA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/OzakiYSIKANUNK11,
author = {Nobuaki Ozaki and
Yoshihiro Yasuda and
Yoshiki Saito and
Daisuke Ikebuchi and
Masayuki Kimura and
Hideharu Amano and
Hiroshi Nakamura and
Kimiyoshi Usami and
Mitaro Namiki and
Masaaki Kondo},
editor = {Russell Tessier},
title = {Cool Mega-Array: {A} highly energy efficient reconfigurable accelerator},
booktitle = {2011 International Conference on Field-Programmable Technology, {FPT}
2011, New Delhi, India, December 12-14, 2011},
pages = {1--8},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/FPT.2011.6132668},
doi = {10.1109/FPT.2011.6132668},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/OzakiYSIKANUNK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/KoibuchiWMNHMA11,
author = {Michihiro Koibuchi and
Takafumi Watanabe and
Atsushi Minamihata and
Masahiro Nakao and
Tomoyuki Hiroyasu and
Hiroki Matsutani and
Hideharu Amano},
title = {Performance Evaluation of Power-Aware Multi-tree Ethernet for {HPC}
Interconnects},
booktitle = {Second International Conference on Networking and Computing, {ICNC}
2011, November 30 - December 2, 2011, Osaka, Japan},
pages = {50--57},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ICNC.2011.17},
doi = {10.1109/ICNC.2011.17},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/KoibuchiWMNHMA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/ShitaraNYKNYA11,
author = {Akihiro Shitara and
Tetsuya Nakahama and
Masahiro Yamada and
Toshiaki Kamata and
Yuri Nishikawa and
Masato Yoshimi and
Hideharu Amano},
title = {Vegeta: An Implementation and Evaluation of Development-Support Middleware
on Multiple OpenCL Platform},
booktitle = {Second International Conference on Networking and Computing, {ICNC}
2011, November 30 - December 2, 2011, Osaka, Japan},
pages = {141--147},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ICNC.2011.28},
doi = {10.1109/ICNC.2011.28},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/ShitaraNYKNYA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/NakahamaYYA11,
author = {Tetsuya Nakahama and
Masahiro Yamada and
Masato Yoshimi and
Hideharu Amano},
title = {Proposal of Auto {MPI} Expansion Tool for Cell Broadband Engine Cluster},
booktitle = {Second International Conference on Networking and Computing, {ICNC}
2011, November 30 - December 2, 2011, Osaka, Japan},
pages = {166--172},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ICNC.2011.32},
doi = {10.1109/ICNC.2011.32},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/NakahamaYYA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/UsamiGMKIAN11,
author = {Kimiyoshi Usami and
Yuya Goto and
Kensaku Matsunaga and
Satoshi Koyama and
Daisuke Ikebuchi and
Hideharu Amano and
Hiroshi Nakamura},
editor = {Naehyuck Chang and
Hiroshi Nakamura and
Koji Inoue and
Kenichi Osada and
Massimo Poncino},
title = {On-chip detection methodology for break-even time of power gated function
units},
booktitle = {Proceedings of the 2011 International Symposium on Low Power Electronics
and Design, 2011, Fukuoka, Japan, August 1-3, 2011},
pages = {241--246},
publisher = {{IEEE/ACM}},
year = {2011},
url = {http://portal.acm.org/citation.cfm?id=2016858\&\#38;CFID=34981777\&\#38;CFTOKEN=25607807},
timestamp = {Mon, 13 Aug 2012 09:40:34 +0200},
biburl = {https://dblp.org/rec/conf/islped/UsamiGMKIAN11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/MatsutaniTSKONKKA11,
author = {Hiroki Matsutani and
Yasuhiro Take and
Daisuke Sasaki and
Masayuki Kimura and
Yuki Ono and
Yukinori Nishiyama and
Michihiro Koibuchi and
Tadahiro Kuroda and
Hideharu Amano},
editor = {Radu Marculescu and
Michael Kishinevsky and
Ran Ginosar and
Karam S. Chatha},
title = {A vertical bubble flow network using inductive-coupling for 3-D CMPs},
booktitle = {{NOCS} 2011, Fifth {ACM/IEEE} International Symposium on Networks-on-Chip,
Pittsburgh, Pennsylvania, USA, May 1-4, 2011},
pages = {49--56},
publisher = {{ACM/IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1145/1999946.1999955},
doi = {10.1145/1999946.1999955},
timestamp = {Wed, 11 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nocs/MatsutaniTSKONKKA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/HironakaA11,
author = {Kazuei Hironaka and
Hideharu Amano},
editor = {Peter M. Athanas and
J{\"{u}}rgen Becker and
Ren{\'{e}} Cumplido},
title = {Power Centric Application Mapping for Dynamically Reconfigurable Processor
Array with Dual Vdd and Dual Vth},
booktitle = {2011 International Conference on Reconfigurable Computing and FPGAs,
ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011},
pages = {404--409},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ReConFig.2011.70},
doi = {10.1109/RECONFIG.2011.70},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/reconfig/HironakaA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtcsa/WangKYMA11,
author = {Daihan Wang and
Michihiro Koibuchi and
Tomohiro Yoneda and
Hiroki Matsutani and
Hideharu Amano},
title = {A Dynamic Link-Width Optimization for Network-on-Chip},
booktitle = {17th {IEEE} International Conference on Embedded and Real-Time Computing
Systems and Applications, {RTCSA} 2011, Toyama, Japan, August 28-31,
2011, Volume 2},
pages = {106--108},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/RTCSA.2011.60},
doi = {10.1109/RTCSA.2011.60},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rtcsa/WangKYMA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/sp/11/MatsutaniKNA11,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Hiroshi Nakamura and
Hideharu Amano},
editor = {Cristina Silvano and
Marcello Lajolo and
Gianluca Palermo},
title = {Run-Time Power-Gating Techniques for Low-Power On-Chip Networks},
booktitle = {Low Power Networks-on-Chip},
pages = {21--43},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-1-4419-6911-8\_2},
doi = {10.1007/978-1-4419-6911-8\_2},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/books/sp/11/MatsutaniKNA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:series/icas/MatsutaniKKA11,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Tadahiro Kuroda and
Hideharu Amano},
editor = {Abbas Sheibanyrad and
Fr{\'{e}}d{\'{e}}ric P{\'{e}}trot and
Axel Jantsch},
title = {3-D NoC on Inductive Wireless Interconnect},
booktitle = {3D Integration for NoC-based SoC Architectures},
series = {Integrated Circuits and Systems},
pages = {225--248},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-1-4419-7618-5\_10},
doi = {10.1007/978-1-4419-7618-5\_10},
timestamp = {Mon, 06 May 2019 18:53:12 +0200},
biburl = {https://dblp.org/rec/series/icas/MatsutaniKKA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/YamadaOOIOYNFHASO10,
author = {Hideki Yamada and
Yui Ogawa and
Tomonori Ooya and
Tomoya Ishimori and
Yasunori Osana and
Masato Yoshimi and
Yuri Nishikawa and
Akira Funahashi and
Noriko Hiroi and
Hideharu Amano and
Yuichiro Shibata and
Kiyoshi Oguri},
title = {Automatic Pipeline Construction Focused on Similarity of Rate Law
Functions for an FPGA-based Biochemical Simulator},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {244--256},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.244},
doi = {10.2197/IPSJTSLDM.3.244},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/YamadaOOIOYNFHASO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/MorishitaIOFA10,
author = {Hirokazu Morishita and
Kenta Inakagata and
Yasunori Osana and
Naoyuki Fujita and
Hideharu Amano},
title = {Implementation and evaluation of an arithmetic pipeline on {FLOPS-2D:}
multi-FPGA system},
journal = {{SIGARCH} Comput. Archit. News},
volume = {38},
number = {4},
pages = {8--13},
year = {2010},
url = {https://doi.org/10.1145/1926367.1926370},
doi = {10.1145/1926367.1926370},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigarch/MorishitaIOFA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/YoshimiNMHAM10,
author = {Masato Yoshimi and
Yuri Nishikawa and
Mitsunori Miki and
Tomoyuki Hiroyasu and
Hideharu Amano and
Oskar Mencer},
editor = {Phaophak Sirisuk and
Fearghal Morgan and
Tarek A. El{-}Ghazawi and
Hideharu Amano},
title = {A Performance Evaluation of {CUBE:} One-Dimensional 512 {FPGA} Cluster},
booktitle = {Reconfigurable Computing: Architectures, Tools and Applications, 6th
International Symposium, {ARC} 2010, Bangkok, Thailand, March 17-19,
2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5992},
pages = {372--381},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-12133-3\_36},
doi = {10.1007/978-3-642-12133-3\_36},
timestamp = {Fri, 27 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/arc/YoshimiNMHAM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/IkebuchiSKKZASKHUMUTNNK10,
author = {Daisuke Ikebuchi and
Naomi Seki and
Yu Kojima and
M. Kamata and
Lei Zhao and
Hideharu Amano and
Toshiaki Shirai and
Satoshi Koyama and
Tatsunori Hashida and
Y. Umahashi and
Hiroki Masuda and
Kimiyoshi Usami and
Seidai Takeda and
Hiroshi Nakamura and
Mitaro Namiki and
Masaaki Kondo},
title = {Geyser-1: a {MIPS} {R3000} {CPU} core with fine-grained run-time power
gating},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {369--370},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419857},
doi = {10.1109/ASPDAC.2010.5419857},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/IkebuchiSKKZASKHUMUTNNK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SaitoSKTYKA10,
author = {Yoshiki Saito and
Toru Sano and
Masaru Kato and
Vasutan Tunbunheng and
Yoshihiro Yasuda and
Masayuki Kimura and
Hideharu Amano},
title = {MuCCRA-3: a low power dynamically reconfigurable processor array},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {377--378},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419853},
doi = {10.1109/ASPDAC.2010.5419853},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/SaitoSKTYKA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/ToiOAWA10,
author = {Takao Toi and
Takumi Okamoto and
Toru Awashima and
Kazutoshi Wakabayashi and
Hideharu Amano},
editor = {Jinian Bian and
Qiang Zhou and
Peter Athanas and
Yajun Ha and
Kang Zhao},
title = {Wire congestion aware synthesis for a dynamically reconfigurable processor},
booktitle = {Proceedings of the International Conference on Field-Programmable
Technology, {FPT} 2010, 8-10 December 2010, Tsinghua University, Beijing,
China},
pages = {300--303},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/FPT.2010.5681481},
doi = {10.1109/FPT.2010.5681481},
timestamp = {Thu, 01 Feb 2018 14:20:39 +0100},
biburl = {https://dblp.org/rec/conf/fpt/ToiOAWA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/HironakaKSSKTYA10,
author = {Kazuei Hironaka and
Masayuki Kimura and
Yoshiki Saito and
Toru Sano and
Masaru Kato and
Vasutan Tunbunheng and
Yoshihiro Yasuda and
Hideharu Amano},
editor = {Jinian Bian and
Qiang Zhou and
Peter Athanas and
Yajun Ha and
Kang Zhao},
title = {Reducing power consumption for Dynamically Reconfigurable Processor
Array with Partially Fixed Configuration Mapping},
booktitle = {Proceedings of the International Conference on Field-Programmable
Technology, {FPT} 2010, 8-10 December 2010, Tsinghua University, Beijing,
China},
pages = {349--352},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/FPT.2010.5681431},
doi = {10.1109/FPT.2010.5681431},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/HironakaKSSKTYA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/OgawaOOYNFHASO10,
author = {Yui Ogawa and
Tomonori Ooya and
Yasunori Osana and
Masato Yoshimi and
Yuri Nishikawa and
Akira Funahashi and
Noriko Hiroi and
Hideharu Amano and
Yuichiro Shibata and
Kiyoshi Oguri},
editor = {Jinian Bian and
Qiang Zhou and
Peter Athanas and
Yajun Ha and
Kang Zhao},
title = {A datapath classification method for FPGA-based scientific application
accelerator systems},
booktitle = {Proceedings of the International Conference on Field-Programmable
Technology, {FPT} 2010, 8-10 December 2010, Tsinghua University, Beijing,
China},
pages = {441--444},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/FPT.2010.5681455},
doi = {10.1109/FPT.2010.5681455},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/OgawaOOYNFHASO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/green/LeiXIASN10,
author = {Zhao Lei and
Hui Xu and
Daisuke Ikebuchi and
Hideharu Amano and
Tetsuya Sunata and
Mitaro Namiki},
title = {Reducing instruction TLB's leakage power consumption for embedded
processors},
booktitle = {International Green Computing Conference 2010, Chicago, IL, USA, 15-18
August 2010},
pages = {477--484},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/GREENCOMP.2010.5598277},
doi = {10.1109/GREENCOMP.2010.5598277},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/green/LeiXIASN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/UsamiHKYIANKN10,
author = {Kimiyoshi Usami and
Tatsunori Hashida and
Satoshi Koyama and
Tatsuya Yamamoto and
Daisuke Ikebuchi and
Hideharu Amano and
Mitaro Namiki and
Masaaki Kondo and
Hiroshi Nakamura},
title = {Adaptive power gating for function units in a microprocessor},
booktitle = {11th International Symposium on Quality of Electronic Design {(ISQED}
2010), 22-24 March 2010, San Jose, CA, {USA}},
pages = {29--37},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISQED.2010.5450407},
doi = {10.1109/ISQED.2010.5450407},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/UsamiHKYIANKN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/HirataMKA10,
author = {Yuto Hirata and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
editor = {Maurizio Palesi and
Shashi Kumar and
Zhonghai Lu and
{\"{U}}mit Y. Ogras},
title = {A variable-pipeline on-chip router optimized to traffic pattern},
booktitle = {Third International Workshop on Network on Chip Architectures, NoCArc'10,
Atlanta, GA, USA, December 4, 2010},
pages = {57--62},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1921249.1921263},
doi = {10.1145/1921249.1921263},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/HirataMKA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nas/AliagaKMA10,
author = {Jos{\'{e}} Miguel Monta{\~{n}}ana Aliaga and
Michihiro Koibuchi and
Hiroki Matsutani and
Hideharu Amano},
title = {Stabilizing Path Modification of Power-Aware On/Off Interconnection
Networks},
booktitle = {Fifth International Conference on Networking, Architecture, and Storage,
{NAS} 2010, Macau, China, July 15-17, 2010},
pages = {218--227},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/NAS.2010.13},
doi = {10.1109/NAS.2010.13},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nas/AliagaKMA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nas/NishikawaKMA10,
author = {Yuri Nishikawa and
Michihiro Koibuchi and
Hiroki Matsutani and
Hideharu Amano},
title = {A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through
Switching},
booktitle = {Fifth International Conference on Networking, Architecture, and Storage,
{NAS} 2010, Macau, China, July 15-17, 2010},
pages = {431--438},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/NAS.2010.50},
doi = {10.1109/NAS.2010.50},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nas/NishikawaKMA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/MatsutaniKIUNA10,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Daisuke Ikebuchi and
Kimiyoshi Usami and
Hiroshi Nakamura and
Hideharu Amano},
title = {Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs},
booktitle = {{NOCS} 2010, Fourth {ACM/IEEE} International Symposium on Networks-on-Chip,
Grenoble, France, May 3-6, 2010},
pages = {61--68},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/NOCS.2010.16},
doi = {10.1109/NOCS.2010.16},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/MatsutaniKIUNA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/arc/2010,
editor = {Phaophak Sirisuk and
Fearghal Morgan and
Tarek A. El{-}Ghazawi and
Hideharu Amano},
title = {Reconfigurable Computing: Architectures, Tools and Applications, 6th
International Symposium, {ARC} 2010, Bangkok, Thailand, March 17-19,
2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5992},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-12133-3},
doi = {10.1007/978-3-642-12133-3},
isbn = {978-3-642-12132-6},
timestamp = {Tue, 14 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arc/2010.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/WangMKA09,
author = {Daihan Wang and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {A Link Removal Methodology for Application-Specific Networks-on-Chip
on FPGAs},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {92-D},
number = {4},
pages = {575--583},
year = {2009},
url = {https://doi.org/10.1587/transinf.E92.D.575},
doi = {10.1587/TRANSINF.E92.D.575},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/WangMKA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/StubdalKA09,
author = {Iver Stubdal and
Arda Karaduman and
Hideharu Amano},
title = {Code Compression with Split Echo Instructions},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {92-D},
number = {9},
pages = {1650--1656},
year = {2009},
url = {https://doi.org/10.1587/transinf.E92.D.1650},
doi = {10.1587/TRANSINF.E92.D.1650},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/StubdalKA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/MatsutaniKYHA09,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Yutaka Yamada and
D. Frank Hsu and
Hideharu Amano},
title = {Fat H-Tree: {A} Cost-Efficient Tree-Based On-Chip Network},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {20},
number = {8},
pages = {1126--1141},
year = {2009},
url = {https://doi.org/10.1109/TPDS.2008.233},
doi = {10.1109/TPDS.2008.233},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/MatsutaniKYHA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AmanoN09,
author = {Hideharu Amano and
Tadao Nakamura},
title = {Guest Editors' Introduction: {ICFPT} 2007},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {2},
pages = {7:1--7:2},
year = {2009},
url = {https://doi.org/10.1145/1534916.1534917},
doi = {10.1145/1534916.1534917},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AmanoN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/IshimoriYSOYNAFHO09,
author = {Tomoya Ishimori and
Hideki Yamada and
Yuichiro Shibata and
Yasunori Osana and
Masato Yoshimi and
Yuri Nishikawa and
Hideharu Amano and
Akira Funahashi and
Noriko Hiroi and
Kiyoshi Oguri},
editor = {J{\"{u}}rgen Becker and
Roger F. Woods and
Peter M. Athanas and
Fearghal Morgan},
title = {Pipeline Scheduling with Input Port Constraints for an FPGA-Based
Biochemical Simulator},
booktitle = {Reconfigurable Computing: Architectures, Tools and Applications, 5th
International Workshop, {ARC} 2009, Karlsruhe, Germany, March 16-18,
2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5453},
pages = {368--373},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-642-00641-8\_43},
doi = {10.1007/978-3-642-00641-8\_43},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arc/IshimoriYSOYNAFHO09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arcs/LeiXSYHUA09,
author = {Lei Zhao and
Hui Xu and
Naomi Seki and
Yoshiki Saito and
Yohei Hasegawa and
Kimiyoshi Usami and
Hideharu Amano},
editor = {Mladen Berekovic and
Christian M{\"{u}}ller{-}Schloer and
Christian Hochberger and
Stephan Wong},
title = {Cache Controller Design on Ultra Low Leakage Embedded Processors},
booktitle = {Architecture of Computing Systems - {ARCS} 2009, 22nd International
Conference, Delft, The Netherlands, March 10-13, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5455},
pages = {171--182},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-642-00454-4\_18},
doi = {10.1007/978-3-642-00454-4\_18},
timestamp = {Tue, 14 May 2019 10:00:52 +0200},
biburl = {https://dblp.org/rec/conf/arcs/LeiXSYHUA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/Amano09,
author = {Hideharu Amano},
editor = {Toomas P. Plaks},
title = {Japanese Dynamically Reconfigurable Processors},
booktitle = {Proceedings of the 2009 International Conference on Engineering of
Reconfigurable Systems {\&} Algorithms, {ERSA} 2009, July 13-16,
2009, Las Vegas Nevada, {USA}},
pages = {19--28},
publisher = {{CSREA} Press},
year = {2009},
timestamp = {Tue, 03 Nov 2009 10:35:19 +0100},
biburl = {https://dblp.org/rec/conf/ersa/Amano09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/SanoSA09,
author = {Toru Sano and
Yoshiki Saito and
Hideharu Amano},
editor = {Toomas P. Plaks},
title = {Configuration with Self-Configured Datapath: {A} High Speed Configuration
Method for Dynamically Reconfigurable Processors},
booktitle = {Proceedings of the 2009 International Conference on Engineering of
Reconfigurable Systems {\&} Algorithms, {ERSA} 2009, July 13-16,
2009, Las Vegas Nevada, {USA}},
pages = {112--118},
publisher = {{CSREA} Press},
year = {2009},
timestamp = {Tue, 03 Nov 2009 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ersa/SanoSA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/SaitoSKTYA09,
author = {Yoshiki Saito and
Toru Sano and
Masaru Kato and
Vasutan Tunbunheng and
Yoshihiro Yasuda and
Hideharu Amano},
editor = {Toomas P. Plaks},
title = {A Real Chip Evaluation of MuCCRA-3: {A} Low Power Dycamically Reconfigurable
Processor Array},
booktitle = {Proceedings of the 2009 International Conference on Engineering of
Reconfigurable Systems {\&} Algorithms, {ERSA} 2009, July 13-16,
2009, Las Vegas Nevada, {USA}},
pages = {283--286},
publisher = {{CSREA} Press},
year = {2009},
timestamp = {Tue, 03 Nov 2009 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ersa/SaitoSKTYA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/SaitoKSHMSKYNMKA09,
author = {Shotaro Saito and
Yoshinori Kohama and
Yasufumi Sugimori and
Yohei Hasegawa and
Hiroki Matsutani and
Toru Sano and
Kazutaka Kasuga and
Yoichi Yoshida and
Kiichi Niitsu and
Noriyuki Miura and
Tadahiro Kuroda and
Hideharu Amano},
editor = {Martin Danek and
Jiri Kadlec and
Brent E. Nelson},
title = {MuCCRA-Cube: {A} 3D dynamically reconfigurable processor with inductive-coupling
link},
booktitle = {19th International Conference on Field Programmable Logic and Applications,
{FPL} 2009, August 31 - September 2, 2009, Prague, Czech Republic},
pages = {6--11},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/FPL.2009.5272565},
doi = {10.1109/FPL.2009.5272565},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/SaitoKSHMSKYNMKA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/SanoSKA09,
author = {Toru Sano and
Yoshiki Saito and
Masaru Kato and
Hideharu Amano},
editor = {Martin Danek and
Jiri Kadlec and
Brent E. Nelson},
title = {Fine Grain Partial Reconfiguration for energy saving in Dynamically
Reconfigurable Processors},
booktitle = {19th International Conference on Field Programmable Logic and Applications,
{FPL} 2009, August 31 - September 2, 2009, Prague, Czech Republic},
pages = {530--533},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/FPL.2009.5272435},
doi = {10.1109/FPL.2009.5272435},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/SanoSKA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/InakagataMOFA09,
author = {Kenta Inakagata and
Hirokazu Morishita and
Yasunori Osana and
Naoyuki Fujita and
Hideharu Amano},
editor = {Martin Danek and
Jiri Kadlec and
Brent E. Nelson},
title = {Modularizing flux limiter functions for a Computational Fluid Dynamics
accelerator on FPGAs},
booktitle = {19th International Conference on Field Programmable Logic and Applications,
{FPL} 2009, August 31 - September 2, 2009, Prague, Czech Republic},
pages = {654--657},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/FPL.2009.5272347},
doi = {10.1109/FPL.2009.5272347},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/InakagataMOFA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/OoyaYISOOYNFHA09,
author = {Tomonori Ooya and
Hideki Yamada and
Tomoya Ishimori and
Yuichiro Shibata and
Yasunori Osana and
Kiyoshi Oguri and
Masato Yoshimi and
Yuri Nishikawa and
Akira Funahashi and
Noriko Hiroi and
Hideharu Amano},
editor = {Martin Danek and
Jiri Kadlec and
Brent E. Nelson},
title = {Configuring area and performance: Empirical evaluation on an FPGA-based
biochemical simulator},
booktitle = {19th International Conference on Field Programmable Logic and Applications,
{FPL} 2009, August 31 - September 2, 2009, Prague, Czech Republic},
pages = {679--682},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/FPL.2009.5272335},
doi = {10.1109/FPL.2009.5272335},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/OoyaYISOOYNFHA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/HiraiKSA09,
author = {Keiichiro Hirai and
Masaru Kato and
Yoshiki Saito and
Hideharu Amano},
editor = {Neil W. Bergmann and
Oliver Diessel and
Lesley Shannon},
title = {Leakage power reduction for coarse-grained dynamically reconfigurable
processor arrays using Dual Vt cells},
booktitle = {Proceedings of the 2009 International Conference on Field-Programmable
Technology, {FPT} 2009, Sydney, Australia, December 9-11, 2009},
pages = {104--111},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/FPT.2009.5377641},
doi = {10.1109/FPT.2009.5377641},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/HiraiKSA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/MatsutaniKAY09,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano and
Tsutomu Yoshinaga},
title = {Prediction router: Yet another low latency on-chip router architecture},
booktitle = {15th International Conference on High-Performance Computer Architecture
{(HPCA-15} 2009), 14-18 February 2009, Raleigh, North Carolina, {USA}},
pages = {367--378},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/HPCA.2009.4798274},
doi = {10.1109/HPCA.2009.4798274},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hpca/MatsutaniKAY09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icppw/AliagaKMA09,
author = {Jos{\'{e}} Miguel Monta{\~{n}}ana Aliaga and
Michihiro Koibuchi and
Hiroki Matsutani and
Hideharu Amano},
editor = {Leonard Barolli and
Wu{-}chun Feng},
title = {Balanced Dimension-Order Routing for k-ary n-cubes},
booktitle = {{ICPPW} 2009, International Conference on Parallel Processing Workshops,
Vienna, Austria, 22-25 September 2009},
pages = {499--506},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ICPPW.2009.64},
doi = {10.1109/ICPPW.2009.64},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icppw/AliagaKMA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/KoibuchiOMA09,
author = {Michihiro Koibuchi and
Tomohiro Otsuka and
Hiroki Matsutani and
Hideharu Amano},
title = {An on/off link activation method for low-power ethernet in {PC} clusters},
booktitle = {23rd {IEEE} International Symposium on Parallel and Distributed Processing,
{IPDPS} 2009, Rome, Italy, May 23-29, 2009},
pages = {1--11},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/IPDPS.2009.5161069},
doi = {10.1109/IPDPS.2009.5161069},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/KoibuchiOMA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/TuanKMA09,
author = {Vu Manh Tuan and
Naohiro Katsura and
Hiroki Matsutani and
Hideharu Amano},
title = {Evaluation of a multicore reconfigurable architecture with variable
core sizes},
booktitle = {23rd {IEEE} International Symposium on Parallel and Distributed Processing,
{IPDPS} 2009, Rome, Italy, May 23-29, 2009},
pages = {1--8},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/IPDPS.2009.5161225},
doi = {10.1109/IPDPS.2009.5161225},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/TuanKMA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispa/NishikawaKYSMA09,
author = {Yuri Nishikawa and
Michihiro Koibuchi and
Masato Yoshimi and
Akihiro Shitara and
Kenichi Miura and
Hideharu Amano},
title = {Performance Analysis of ClearSpeed's {CSX600} Interconnects},
booktitle = {{IEEE} International Symposium on Parallel and Distributed Processing
with Applications, {ISPA} 2009, Chengdu, Sichuan, China, 10-12 August
2009},
pages = {203--210},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISPA.2009.102},
doi = {10.1109/ISPA.2009.102},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispa/NishikawaKYSMA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdpta/AliagaKWHMA09,
author = {Jos{\'{e}} Miguel Monta{\~{n}}ana Aliaga and
Michihiro Koibuchi and
Takafumi Watanabe and
Tomoyuki Hiroyasu and
Hiroki Matsutani and
Hideharu Amano},
editor = {Hamid R. Arabnia},
title = {An On/Off Link Activation Method for Power Regulation in InfiniBand},
booktitle = {Proceedings of the International Conference on Parallel and Distributed
Processing Techniques and Applications, {PDPTA} 2009, Las Vegas, Nevada,
USA, July 13-17, 2009, 2 Volumes},
pages = {289--295},
publisher = {{CSREA} Press},
year = {2009},
timestamp = {Wed, 02 Feb 2011 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/pdpta/AliagaKWHMA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/YamadaOIOYNFHASO09,
author = {Hideki Yamada and
Yasunori Osana and
Tomoya Ishimori and
Tomonori Ooya and
Masato Yoshimi and
Yuri Nishikawa and
Akira Funahashi and
Noriko Hiroi and
Hideharu Amano and
Yuichiro Shibata and
Kiyoshi Oguri},
editor = {Viktor K. Prasanna and
Lionel Torres and
Ren{\'{e}} Cumplido},
title = {A Modular Approach to Heterogeneous Biochemical Model Simulation on
an {FPGA}},
booktitle = {ReConFig'09: 2009 International Conference on Reconfigurable Computing
and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings},
pages = {125--130},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ReConFig.2009.55},
doi = {10.1109/RECONFIG.2009.55},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/YamadaOIOYNFHASO09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/UsamiSHMTNSANIKN09,
author = {Kimiyoshi Usami and
Toshiaki Shirai and
Tatsunori Hashida and
Hiroki Masuda and
Seidai Takeda and
Mitsutaka Nakata and
Naomi Seki and
Hideharu Amano and
Mitaro Namiki and
Masashi Imai and
Masaaki Kondo and
Hiroshi Nakamura},
title = {Design and Implementation of Fine-Grain Power Gating with Ground Bounce
Suppression},
booktitle = {{VLSI} Design 2009: Improving Productivity through Higher Abstraction,
The 22nd International Conference on {VLSI} Design, New Delhi, India,
5-9 January 2009},
pages = {381--386},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/VLSI.Design.2009.63},
doi = {10.1109/VLSI.DESIGN.2009.63},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/UsamiSHMTNSANIKN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TuanA08,
author = {Vu Manh Tuan and
Hideharu Amano},
title = {A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable
Processors},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {91-D},
number = {9},
pages = {2312--2322},
year = {2008},
url = {https://doi.org/10.1093/ietisy/e91-d.9.2312},
doi = {10.1093/IETISY/E91-D.9.2312},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/TuanA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TunbunhengA08,
author = {Vasutan Tunbunheng and
Hideharu Amano},
title = {A Retargetable Compiler Based on Graph Representation for Dynamically
Reconfigurable Processor Arrays},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {91-D},
number = {11},
pages = {2655--2665},
year = {2008},
url = {https://doi.org/10.1093/ietisy/e91-d.11.2655},
doi = {10.1093/IETISY/E91-D.11.2655},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/TunbunhengA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TuanA08a,
author = {Vu Manh Tuan and
Hideharu Amano},
title = {A Preemption Algorithm for a Multitasking Environment on Dynamically
Reconfigurable Processors},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {91-D},
number = {12},
pages = {2793--2803},
year = {2008},
url = {https://doi.org/10.1093/ietisy/e91-d.12.2793},
doi = {10.1093/IETISY/E91-D.12.2793},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/TuanA08a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/TuanA08,
author = {Vu Manh Tuan and
Hideharu Amano},
editor = {Roger F. Woods and
Katherine Compton and
Christos{-}Savvas Bouganis and
Pedro C. Diniz},
title = {A Preemption Algorithm for a Multitasking Environment on Dynamically
Reconfigurable Processor},
booktitle = {Reconfigurable Computing: Architectures, Tools and Applications, 4th
International Workshop, {ARC} 2008, London, UK, March 26-28, 2008.
Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4943},
pages = {171--182},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-78610-8\_18},
doi = {10.1007/978-3-540-78610-8\_18},
timestamp = {Tue, 14 May 2019 10:00:49 +0200},
biburl = {https://dblp.org/rec/conf/arc/TuanA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/MatsutaniKAW08,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano and
Daihan Wang},
editor = {Chong{-}Min Kyung and
Kiyoung Choi and
Soonhoi Ha},
title = {Run-time power gating of on-chip routers using look-ahead routing},
booktitle = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
pages = {55--60},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ASPDAC.2008.4484015},
doi = {10.1109/ASPDAC.2008.4484015},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/MatsutaniKAW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/TuanA08,
author = {Vu Manh Tuan and
Hideharu Amano},
editor = {Toomas P. Plaks},
title = {A Method for Capturing State Data on Dynamically Reconfigurable Processors},
booktitle = {Proceedings of the 2008 International Conference on Engineering of
Reconfigurable Systems {\&} Algorithms, {ERSA} 2008, Las Vegas,
Nevada, USA, July 14-17, 2008},
pages = {208--214},
publisher = {{CSREA} Press},
year = {2008},
timestamp = {Thu, 12 Feb 2009 10:30:38 +0100},
biburl = {https://dblp.org/rec/conf/ersa/TuanA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/KatoHA08,
author = {Masaru Kato and
Yohei Hasegawa and
Hideharu Amano},
editor = {Toomas P. Plaks},
title = {Evaluation of MuCCRA-D: {A} Dynamically Reconfigurable Processor with
Directly Interconnected PEs},
booktitle = {Proceedings of the 2008 International Conference on Engineering of
Reconfigurable Systems {\&} Algorithms, {ERSA} 2008, Las Vegas,
Nevada, USA, July 14-17, 2008},
pages = {215--221},
publisher = {{CSREA} Press},
year = {2008},
timestamp = {Thu, 12 Feb 2009 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ersa/KatoHA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/SanoKTHA08,
author = {Toru Sano and
Masaru Kato and
Satoshi Tsutsumi and
Yohei Hasegawa and
Hideharu Amano},
title = {Instruction buffer mode for multi-context Dynamically Reconfigurable
Processors},
booktitle = {{FPL} 2008, International Conference on Field Programmable Logic and
Applications, Heidelberg, Germany, 8-10 September 2008},
pages = {215--220},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FPL.2008.4629934},
doi = {10.1109/FPL.2008.4629934},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/SanoKTHA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/WangMAK08,
author = {Daihan Wang and
Hiroki Matsutani and
Hideharu Amano and
Michihiro Koibuchi},
title = {A link removal methodology for Networks-on-Chip on reconfigurable
systems},
booktitle = {{FPL} 2008, International Conference on Field Programmable Logic and
Applications, Heidelberg, Germany, 8-10 September 2008},
pages = {269--274},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FPL.2008.4629943},
doi = {10.1109/FPL.2008.4629943},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/WangMAK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/NishimuraHSNHTTA08,
author = {Takashi Nishimura and
Keiichiro Hirai and
Yoshiki Saito and
Takuro Nakamura and
Yohei Hasegawa and
Satoshi Tsutsumi and
Vasutan Tunbunheng and
Hideharu Amano},
title = {Power reduction techniques for Dynamically Reconfigurable Processor
Arrays},
booktitle = {{FPL} 2008, International Conference on Field Programmable Logic and
Applications, Heidelberg, Germany, 8-10 September 2008},
pages = {305--310},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FPL.2008.4629949},
doi = {10.1109/FPL.2008.4629949},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/NishimuraHSNHTTA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/YoshimiNOFSYHKA08,
author = {Masato Yoshimi and
Yuri Nishikawa and
Yasunori Osana and
Akira Funahashi and
Yuichiro Shibata and
Hideki Yamada and
Noriko Hiroi and
Hiroaki Kitano and
Hideharu Amano},
title = {Practical implementation of a network-based stochastic biochemical
simulation system on an {FPGA}},
booktitle = {{FPL} 2008, International Conference on Field Programmable Logic and
Applications, Heidelberg, Germany, 8-10 September 2008},
pages = {663--666},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FPL.2008.4630034},
doi = {10.1109/FPL.2008.4630034},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/YoshimiNOFSYHKA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/NakamuraSHTTA08,
author = {Takuro Nakamura and
Toru Sano and
Yohei Hasegawa and
Satoshi Tsutsumi and
Vasutan Tunbunheng and
Hideharu Amano},
editor = {Tarek A. El{-}Ghazawi and
Yao{-}Wen Chang and
Juinn{-}Dar Huang and
Proshanta Saha},
title = {Exploring the optimal size for multicasting configuration data of
dynamically reconfigurable processors},
booktitle = {2008 International Conference on Field-Programmable Technology, {FPT}
2008, Taipei, Taiwan, December 7-10, 2008},
pages = {137--144},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FPT.2008.4762376},
doi = {10.1109/FPT.2008.4762376},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/NakamuraSHTTA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/MorishitaOFA08,
author = {Hirokazu Morishita and
Yasunori Osana and
Naoyuki Fujita and
Hideharu Amano},
editor = {Tarek A. El{-}Ghazawi and
Yao{-}Wen Chang and
Juinn{-}Dar Huang and
Proshanta Saha},
title = {Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator
on FPGAs},
booktitle = {2008 International Conference on Field-Programmable Technology, {FPT}
2008, Taipei, Taiwan, December 7-10, 2008},
pages = {193--200},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FPT.2008.4762383},
doi = {10.1109/FPT.2008.4762383},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/MorishitaOFA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/SaitoSNNHTKNTUA08,
author = {Yoshiki Saito and
Tomoaki Shirai and
Takuro Nakamura and
Takashi Nishimura and
Yohei Hasegawa and
Satoshi Tsutsumi and
Toshihiro Kashima and
Mitsutaka Nakata and
Seidai Takeda and
Kimiyoshi Usami and
Hideharu Amano},
editor = {Tarek A. El{-}Ghazawi and
Yao{-}Wen Chang and
Juinn{-}Dar Huang and
Proshanta Saha},
title = {Leakage power reduction for coarse grained dynamically reconfigurable
processor arrays with fine grained Power Gating technique},
booktitle = {2008 International Conference on Field-Programmable Technology, {FPT}
2008, Taipei, Taiwan, December 7-10, 2008},
pages = {329--332},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FPT.2008.4762410},
doi = {10.1109/FPT.2008.4762410},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/SaitoSNNHTKNTUA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/SekiZKIKHAKTSNUSKNKN08,
author = {Naomi Seki and
Lei Zhao and
Jo Kei and
Daisuke Ikebuchi and
Yu Kojima and
Yohei Hasegawa and
Hideharu Amano and
Toshihiro Kashima and
Seidai Takeda and
Toshiaki Shirai and
Mitsutaka Nakata and
Kimiyoshi Usami and
Tetsuya Sunata and
Jun Kanai and
Mitaro Namiki and
Masaaki Kondo and
Hiroshi Nakamura},
title = {A fine-grain dynamic sleep control scheme in {MIPS} {R3000}},
booktitle = {26th International Conference on Computer Design, {ICCD} 2008, 12-15
October 2008, Lake Tahoe, CA, USA, Proceedings},
pages = {612--617},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ICCD.2008.4751924},
doi = {10.1109/ICCD.2008.4751924},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/SekiZKIKHAKTSNUSKNKN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispan/MatsutaniKHA08,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
D. Frank Hsu and
Hideharu Amano},
title = {Three-Dimensional Layout of On-Chip Tree-Based Networks},
booktitle = {9th International Symposium on Parallel Architectures, Algorithms,
and Networks, {ISPAN} 2008, 7-9 May 2008, Sydney, NSW, Australia},
pages = {281--288},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/I-SPAN.2008.39},
doi = {10.1109/I-SPAN.2008.39},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispan/MatsutaniKHA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/KoibuchiMAP08,
author = {Michihiro Koibuchi and
Hiroki Matsutani and
Hideharu Amano and
Timothy Mark Pinkston},
title = {A Lightweight Fault-Tolerant Mechanism for Network-on-Chip},
booktitle = {Second International Symposium on Networks-on-Chips, {NOCS} 2008,
5-6 April 2008, Newcastle University, {UK.} Proceedings},
pages = {13--22},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.ieeecomputersociety.org/10.1109/NOCS.2008.34},
doi = {10.1109/NOCS.2008.34},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/KoibuchiMAP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/MatsutaniKWA08,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Daihan Wang and
Hideharu Amano},
title = {Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks},
booktitle = {Second International Symposium on Networks-on-Chips, {NOCS} 2008,
5-6 April 2008, Newcastle University, {UK.} Proceedings},
pages = {23--32},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.ieeecomputersociety.org/10.1109/NOCS.2008.18},
doi = {10.1109/NOCS.2008.18},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/MatsutaniKWA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/KishimotoHA08,
author = {Yuken Kishimoto and
Shinichiro Haruyama and
Hideharu Amano},
title = {Design and Implementation of Adaptive Viterbi Decoder for Using {A}
Dynamic Reconfigurable Processor},
booktitle = {ReConFig'08: 2008 International Conference on Reconfigurable Computing
and FPGAs, 3-5 December 2008, Cancun, Mexico, Proceedings},
pages = {247--252},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ReConFig.2008.39},
doi = {10.1109/RECONFIG.2008.39},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/reconfig/KishimotoHA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TunbunhengSA07,
author = {Vasutan Tunbunheng and
Masayasu Suzuki and
Hideharu Amano},
title = {Data Multicasting Procedure for Increasing Configuration Speed of
Coarse Grain Reconfigurable Devices},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {90-D},
number = {2},
pages = {473--481},
year = {2007},
url = {https://doi.org/10.1093/ietisy/e90-d.2.473},
doi = {10.1093/IETISY/E90-D.2.473},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/TunbunhengSA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/WangMKA07,
author = {Daihan Wang and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {A Port Combination Methodology for Application-Specific Networks-on-Chip
on FPGAs},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {90-D},
number = {12},
pages = {1914--1922},
year = {2007},
url = {https://doi.org/10.1093/ietisy/e90-d.12.1914},
doi = {10.1093/IETISY/E90-D.12.1914},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/WangMKA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/JourakuKA07,
author = {Akiya Jouraku and
Michihiro Koibuchi and
Hideharu Amano},
title = {An Effective Design of Deadlock-Free Routing Algorithms Based on 2D
Turn Model for Irregular Networks},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {18},
number = {3},
pages = {320--333},
year = {2007},
url = {https://doi.org/10.1109/TPDS.2007.36},
doi = {10.1109/TPDS.2007.36},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/JourakuKA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/WatanabeOTNYTKA07,
author = {Konosuke Watanabe and
Tomohiro Otsuka and
Junichiro Tsuchiya and
Hiroaki Nishi and
Junji Yamamoto and
Noboru Tanabe and
Tomohiro Kudoh and
Hideharu Amano},
title = {Martini: {A} Network Interface Controller Chip for High Performance
Computing with Distributed PCs},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {18},
number = {9},
pages = {1282--1295},
year = {2007},
url = {https://doi.org/10.1109/TPDS.2007.1064},
doi = {10.1109/TPDS.2007.1064},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/WatanabeOTNYTKA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEcit/KanamoriAAKNA07,
author = {Takamasa Kanamori and
Hideharu Amano and
Masatoshi Arai and
Daisuke Konno and
Tomomichi Nanba and
Yoshiaki Ajioka},
title = {Implementation and Evaluation of a High Speed License Plate Recognition
System on an {FPGA}},
booktitle = {Seventh International Conference on Computer and Information Technology
{(CIT} 2007), October 16-19, 2007, University of Aizu, Fukushima,
Japan},
pages = {567--572},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/CIT.2007.167},
doi = {10.1109/CIT.2007.167},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/IEEEcit/KanamoriAAKNA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/TuanHA07,
author = {Vu Manh Tuan and
Yohei Hasegawa and
Hideharu Amano},
editor = {Toomas P. Plaks},
title = {Performance Analysis of Multi-process Execution Model on Dynamically
Reconfigurable Processor},
booktitle = {Proceedings of the 2007 International Conference on Engineering of
Reconfigurable Systems {\&} Algorithms, {ERSA} 2007, Las Vegas,
Nevada, USA, June 25-28, 2007},
pages = {203--206},
publisher = {{CSREA} Press},
year = {2007},
timestamp = {Fri, 14 Dec 2007 20:45:54 +0100},
biburl = {https://dblp.org/rec/conf/ersa/TuanHA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/YoshimiINKOFHSIYKA07,
author = {Masato Yoshimi and
Yow Iwaoka and
Yuri Nishikawa and
Toshinori Kojima and
Yasunori Osana and
Akira Funahashi and
Noriko Hiroi and
Yuichiro Shibata and
Naoki Iwanaga and
Hideki Yamada and
Hiroaki Kitano and
Hideharu Amano},
editor = {Koen Bertels and
Walid A. Najjar and
Arjan J. van Genderen and
Stamatis Vassiliadis},
title = {{FPGA} Implementation of a Data-Driven Stochastic Biochemical Simulator
with the Next Reaction Method},
booktitle = {{FPL} 2007, International Conference on Field Programmable Logic and
Applications, Amsterdam, The Netherlands, 27-29 August 2007},
pages = {254--259},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/FPL.2007.4380656},
doi = {10.1109/FPL.2007.4380656},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/YoshimiINKOFHSIYKA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/WangMKA07,
author = {Daihan Wang and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
editor = {Koen Bertels and
Walid A. Najjar and
Arjan J. van Genderen and
Stamatis Vassiliadis},
title = {A Temporal Correlation Based Port Combination Methodology for Networks-on-chip
on Reconfigurable Systems},
booktitle = {{FPL} 2007, International Conference on Field Programmable Logic and
Applications, Amsterdam, The Netherlands, 27-29 August 2007},
pages = {383--388},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/FPL.2007.4380676},
doi = {10.1109/FPL.2007.4380676},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/WangMKA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KanamoriAAKNA07,
author = {Takamasa Kanamori and
Hideharu Amano and
Masatoshi Arai and
Daisuke Konno and
Tomomichi Nanba and
Yoshiaki Ajioka},
editor = {Koen Bertels and
Walid A. Najjar and
Arjan J. van Genderen and
Stamatis Vassiliadis},
title = {A High Speed License Plate Recognition System on an {FPGA}},
booktitle = {{FPL} 2007, International Conference on Field Programmable Logic and
Applications, Amsterdam, The Netherlands, 27-29 August 2007},
pages = {554--557},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/FPL.2007.4380715},
doi = {10.1109/FPL.2007.4380715},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/KanamoriAAKNA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/HasegawaA07,
author = {Yohei Hasegawa and
Hideharu Amano},
editor = {Koen Bertels and
Walid A. Najjar and
Arjan J. van Genderen and
Stamatis Vassiliadis},
title = {Design Methodology and Trade-offs Analysis for Parameterized Dynamically
Reconfigurable Processor Arrays},
booktitle = {{FPL} 2007, International Conference on Field Programmable Logic and
Applications, Amsterdam, The Netherlands, 27-29 August 2007},
pages = {796--799},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/FPL.2007.4380771},
doi = {10.1109/FPL.2007.4380771},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/HasegawaA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/YamadaISOYINKAFHKO07,
author = {Hideki Yamada and
Naoki Iwanaga and
Yuichiro Shibata and
Yasunori Osana and
Masato Yoshimi and
Yow Iwaoka and
Yuri Nishikawa and
Toshinori Kojima and
Hideharu Amano and
Akira Funahashi and
Noriko Hiroi and
Hiroaki Kitano and
Kiyoshi Oguri},
editor = {Koen Bertels and
Walid A. Najjar and
Arjan J. van Genderen and
Stamatis Vassiliadis},
title = {A Combining technique of rate law functions for a cost-effective reconfigurable
biological simulator},
booktitle = {{FPL} 2007, International Conference on Field Programmable Logic and
Applications, Amsterdam, The Netherlands, 27-29 August 2007},
pages = {808--811},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/FPL.2007.4380774},
doi = {10.1109/FPL.2007.4380774},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/YamadaISOYINKAFHKO07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/YoshimiNKOFHSYKA07,
author = {Masato Yoshimi and
Yuri Nishikawa and
Toshinori Kojima and
Yasunori Osana and
Akira Funahashi and
Noriko Hiroi and
Yuichiro Shibata and
Hideki Yamada and
Hiroaki Kitano and
Hideharu Amano},
editor = {Hideharu Amano and
Andy Ye and
Takeshi Ikenaga},
title = {A Framework for Implementing a Network-Based Stochastic Biochemical
Simulator on an {FPGA}},
booktitle = {2007 International Conference on Field-Programmable Technology, {ICFPT}
2007, Kitakyushu, Japan, December 12-14, 2007},
pages = {193--200},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/FPT.2007.4439249},
doi = {10.1109/FPT.2007.4439249},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/YoshimiNKOFHSYKA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/TsutsumiTHPNNA07,
author = {Satoshi Tsutsumi and
Vasutan Tunbunheng and
Yohei Hasegawa and
Adepu Parimala and
Takuro Nakamura and
Takashi Nishimura and
Hideharu Amano},
editor = {Hideharu Amano and
Andy Ye and
Takeshi Ikenaga},
title = {Overwrite Configuration Technique in Multicast Configuration Scheme
for Dynamically Reconfigurable Processor Arrays},
booktitle = {2007 International Conference on Field-Programmable Technology, {ICFPT}
2007, Kitakyushu, Japan, December 12-14, 2007},
pages = {273--276},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/FPT.2007.4439264},
doi = {10.1109/FPT.2007.4439264},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/TsutsumiTHPNNA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/TuanA07,
author = {Vu Manh Tuan and
Hideharu Amano},
editor = {Hideharu Amano and
Andy Ye and
Takeshi Ikenaga},
title = {A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable
Processors},
booktitle = {2007 International Conference on Field-Programmable Technology, {ICFPT}
2007, Kitakyushu, Japan, December 12-14, 2007},
pages = {357--360},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/FPT.2007.4439285},
doi = {10.1109/FPT.2007.4439285},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/TuanA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/MatsutaniKA07,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {Tightly-Coupled Multi-Layer Topologies for 3-D NoCs},
booktitle = {2007 International Conference on Parallel Processing {(ICPP} 2007),
September 10-14, 2007, Xi-An, China},
pages = {75},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ICPP.2007.79},
doi = {10.1109/ICPP.2007.79},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpp/MatsutaniKA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/NishikawaKYMA07,
author = {Yuri Nishikawa and
Michihiro Koibuchi and
Masato Yoshimi and
Kenichi Miura and
Hideharu Amano},
title = {Performance Improvement Methodology for ClearSpeed's {CSX600}},
booktitle = {2007 International Conference on Parallel Processing {(ICPP} 2007),
September 10-14, 2007, Xi-An, China},
pages = {77},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ICPP.2007.66},
doi = {10.1109/ICPP.2007.66},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpp/NishikawaKYMA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/MatsutaniKA07,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {Performance, Cost, and Energy Evaluation of Fat H-Tree: {A} Cost-Efficient
Tree-Based On-Chip Network},
booktitle = {21th International Parallel and Distributed Processing Symposium {(IPDPS}
2007), Proceedings, 26-30 March 2007, Long Beach, California, {USA}},
pages = {1--10},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/IPDPS.2007.370271},
doi = {10.1109/IPDPS.2007.370271},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/MatsutaniKA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdcn/KitamuraMMTNA07,
author = {Akira Kitamura and
Yasuo Miyabe and
Tomotaka Miyashiro and
Noboru Tanabe and
Hironori Nakajo and
Hideharu Amano},
editor = {Helmar Burkhart},
title = {Performance evaluation on low-latency communication mechanism of DIMMnet-2},
booktitle = {Proceedings of the {IASTED} International Conference on Parallel and
Distributed Computing and Networks, as part of the 25th {IASTED} International
Multi-Conference on Applied Informatics, February 13-15 2007, Innsbruck,
Austria},
pages = {57--62},
publisher = {{IASTED/ACTA} Press},
year = {2007},
timestamp = {Thu, 25 Oct 2007 15:04:30 +0200},
biburl = {https://dblp.org/rec/conf/pdcn/KitamuraMMTNA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdpta/OhtaHKTAN07,
author = {Atsushi Ohta and
Yoshihiro Hamada and
Akira Kitamura and
Noboru Tanabe and
Hideharu Amano and
Hironori Nakajo},
editor = {Hamid R. Arabnia},
title = {Implementation and Evaluation of Multicast Mechanism on Network Interface
Plugged into a Memory Slot},
booktitle = {Proceedings of the International Conference on Parallel and Distributed
Processing Techniques and Applications, {PDPTA} 2007, Las Vegas, Nevada,
USA, June 25-28, 2007, Volume 2},
pages = {787--793},
publisher = {{CSREA} Press},
year = {2007},
timestamp = {Tue, 17 Jan 2012 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/pdpta/OhtaHKTAN07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fpt/2007,
editor = {Hideharu Amano and
Andy Ye and
Takeshi Ikenaga},
title = {2007 International Conference on Field-Programmable Technology, {ICFPT}
2007, Kitakyushu, Japan, December 12-14, 2007},
publisher = {{IEEE}},
year = {2007},
url = {https://ieeexplore.ieee.org/xpl/conhome/4439213/proceeding},
isbn = {1-4244-1472-5},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/2007.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/Amano06,
author = {Hideharu Amano},
title = {A Survey on Dynamically Reconfigurable Processors},
journal = {{IEICE} Trans. Commun.},
volume = {89-B},
number = {12},
pages = {3179--3187},
year = {2006},
url = {https://doi.org/10.1093/ietcom/e89-b.12.3179},
doi = {10.1093/IETCOM/E89-B.12.3179},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/Amano06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/KoibuchiAYJA06,
author = {Michihiro Koibuchi and
Kenichiro Anjo and
Yutaka Yamada and
Akiya Jouraku and
Hideharu Amano},
title = {A Simple Data Transfer Technique Using Local Address for Networks-on-Chips},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {17},
number = {12},
pages = {1425--1437},
year = {2006},
url = {https://doi.org/10.1109/TPDS.2006.166},
doi = {10.1109/TPDS.2006.166},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/KoibuchiAYJA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ISCApdcs/MatsutaniKA06,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
editor = {Gregory D. Peterson},
title = {A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus
Networks},
booktitle = {Proceedings of the {ISCA} 19th International Conference on Parallel
and Distributed Computing Systems, September 20-11, 2006, San Francisco,
California, {USA}},
pages = {24--31},
publisher = {{ISCA}},
year = {2006},
timestamp = {Mon, 09 Aug 2021 16:35:46 +0200},
biburl = {https://dblp.org/rec/conf/ISCApdcs/MatsutaniKA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/TuanHKA06,
author = {Vu Manh Tuan and
Yohei Hasegawa and
Naohiro Katsura and
Hideharu Amano},
editor = {Koen Bertels and
Jo{\~{a}}o M. P. Cardoso and
Stamatis Vassiliadis},
title = {Performance/Cost Trade-Off Evaluation for the {DCT} Implementation
on the Dynamically Reconfigurable Processor},
booktitle = {Reconfigurable Computing: Architectures and Applications, Second International
Workshop, {ARC} 2006, Delft, The Netherlands, March 1-3, 2006, Revised
Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {3985},
pages = {115--121},
publisher = {Springer},
year = {2006},
url = {https://doi.org/10.1007/11802839\_16},
doi = {10.1007/11802839\_16},
timestamp = {Tue, 14 May 2019 10:00:49 +0200},
biburl = {https://dblp.org/rec/conf/arc/TuanHKA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/WangMYKA06,
author = {Daihan Wang and
Hiroki Matsutani and
Masato Yoshimi and
Michihiro Koibuchi and
Hideharu Amano},
editor = {Toomas P. Plaks},
title = {A Parametric Study of Scalable Interconnects on FPGAs},
booktitle = {Proceedings of the 2006 International Conference on Engineering of
Reconfigurable Systems {\&} Algorithms, {ERSA} 2006, Las Vegas,
Nevada, USA, June 26-29, 2006},
pages = {130--135},
publisher = {{CSREA} Press},
year = {2006},
timestamp = {Mon, 11 Dec 2006 15:00:43 +0100},
biburl = {https://dblp.org/rec/conf/ersa/WangMYKA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/AmanoHAITKNN06,
author = {Hideharu Amano and
Yohei Hasegawa and
Shohei Abe and
Kenichiro Ishikawa and
Shunsuke Tsutsumi and
Shunsuke Kurotaki and
Takuro Nakamura and
Takashi Nishimura},
title = {A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable
Processors},
booktitle = {Proceedings of the 2006 International Conference on Field Programmable
Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006},
pages = {1--6},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/FPL.2006.311269},
doi = {10.1109/FPL.2006.311269},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/AmanoHAITKNN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/OsanaYFHSIKA06,
author = {Yasunori Osana and
Masato Yoshimi and
Akira Funahashi and
Noriko Hiroi and
Yuichiro Shibata and
Naoki Iwanaga and
Hiroaki Kitano and
Hideharu Amano},
title = {Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip},
booktitle = {Proceedings of the 2006 International Conference on Field Programmable
Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006},
pages = {1--6},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/FPL.2006.311327},
doi = {10.1109/FPL.2006.311327},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/OsanaYFHSIKA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/YoshimiOINKFHSIKA06,
author = {Masato Yoshimi and
Yasunori Osana and
Yow Iwaoka and
Yuri Nishikawa and
Toshinori Kojima and
Akira Funahashi and
Noriko Hiroi and
Yuichiro Shibata and
Naoki Iwanaga and
Hiroaki Kitano and
Hideharu Amano},
title = {An {FPGA} Implementation of High Throughput Stochastic Simulator for
Large-Scale Biochemical Systems},
booktitle = {Proceedings of the 2006 International Conference on Field Programmable
Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006},
pages = {1--6},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/FPL.2006.311218},
doi = {10.1109/FPL.2006.311218},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/YoshimiOINKFHSIKA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/AbeHTIA06,
author = {Shohei Abe and
Yohei Hasegawa and
Takao Toi and
Takeshi Inuo and
Hideharu Amano},
editor = {George A. Constantinides and
Wai{-}Kei Mak and
Phaophak Sirisuk and
Theerayod Wiangtong},
title = {An adaptive Viterbi decoder on the dynamically reconfigurable processor},
booktitle = {2006 {IEEE} International Conference on Field Programmable Technology,
{FPT} 2006, Bangkok, Thailand, December 13-15, 2006},
pages = {285--288},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/FPT.2006.270329},
doi = {10.1109/FPT.2006.270329},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/AbeHTIA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/OtsukaKKA06,
author = {Tomohiro Otsuka and
Michihiro Koibuchi and
Tomohiro Kudoh and
Hideharu Amano},
title = {Switch-tagged {VLAN} Routing Methodology for {PC} Clusters with Ethernet},
booktitle = {2006 International Conference on Parallel Processing {(ICPP} 2006),
14-18 August 2006, Columbus, Ohio, {USA}},
pages = {479--486},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ICPP.2006.67},
doi = {10.1109/ICPP.2006.67},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpp/OtsukaKKA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/HasegawaAKTKNNA06,
author = {Yohei Hasegawa and
Shohei Abe and
Shunsuke Kurotaki and
Vu Manh Tuan and
Naohiro Katsura and
Takuro Nakamura and
Takashi Nishimura and
Hideharu Amano},
title = {Performance and power analysis of time-multiplexed execution on dynamically
reconfigurable processor},
booktitle = {20th International Parallel and Distributed Processing Symposium {(IPDPS}
2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/IPDPS.2006.1639431},
doi = {10.1109/IPDPS.2006.1639431},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/HasegawaAKTKNNA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/SuzukiHTAA06,
author = {Masayasu Suzuki and
Yohei Hasegawa and
Vu Manh Tuan and
Shohei Abe and
Hideharu Amano},
title = {A cost-effective context memory structure for dynamically reconfigurable
processors},
booktitle = {20th International Parallel and Distributed Processing Symposium {(IPDPS}
2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/IPDPS.2006.1639433},
doi = {10.1109/IPDPS.2006.1639433},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/SuzukiHTAA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispa/MatsutaniKA06,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
editor = {Minyi Guo and
Laurence Tianruo Yang and
Beniamino Di Martino and
Hans P. Zima and
Jack J. Dongarra and
Feilong Tang},
title = {Enforcing Dimension-Order Routing in On-Chip Torus Networks Without
Virtual Channels},
booktitle = {Parallel and Distributed Processing and Applications, 4th International
Symposium, {ISPA} 2006, Sorrento, Italy, December 4-6, 2006, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4330},
pages = {207--218},
publisher = {Springer},
year = {2006},
url = {https://doi.org/10.1007/11946441\_23},
doi = {10.1007/11946441\_23},
timestamp = {Tue, 14 May 2019 10:00:40 +0200},
biburl = {https://dblp.org/rec/conf/ispa/MatsutaniKA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KoibuchiJA05,
author = {Michihiro Koibuchi and
Akiya Jouraku and
Hideharu Amano},
title = {{MMLRU} Selection Function: {A} Simple and Efficient Output Selection
Function in Adaptive Routing},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {88-D},
number = {1},
pages = {109--118},
year = {2005},
url = {http://search.ieice.org/bin/summary.php?id=e88-d\_1\_109\&\#38;category=D\&\#38;year=2005\&\#38;lang=E\&\#38;abst=},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KoibuchiJA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pc/KoibuchiJA05,
author = {Michihiro Koibuchi and
Akiya Jouraku and
Hideharu Amano},
title = {Path selection algorithm: the strategy for designing deterministic
routing from alternative paths},
journal = {Parallel Comput.},
volume = {31},
number = {1},
pages = {117--130},
year = {2005},
url = {https://doi.org/10.1016/j.parco.2004.11.003},
doi = {10.1016/J.PARCO.2004.11.003},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/pc/KoibuchiJA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pc/MidorikawaSSTHA05,
author = {Takashi Midorikawa and
Daisuke Shiraishi and
Masayoshi Shigeno and
Yasuki Tanabe and
Toshihiro Hanawa and
Hideharu Amano},
title = {The performance of {SNAIL-2} (a {SSS-MIN} connected multiprocessor
with cache coherent mechanism)},
journal = {Parallel Comput.},
volume = {31},
number = {3-4},
pages = {352--370},
year = {2005},
url = {https://doi.org/10.1016/j.parco.2004.11.004},
doi = {10.1016/J.PARCO.2004.11.004},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/pc/MidorikawaSSTHA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/KoibuchiWOA05,
author = {Michihiro Koibuchi and
Konosuke Watanabe and
Tomohiro Otsuka and
Hideharu Amano},
title = {Performance Evaluation of Deterministic Routings, Multicasts, and
Topologies on RHiNET-2 Cluster},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {16},
number = {8},
pages = {747--759},
year = {2005},
url = {https://doi.org/10.1109/TPDS.2005.97},
doi = {10.1109/TPDS.2005.97},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/KoibuchiWOA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arcs/DeguchiASAAA05,
author = {Katsuaki Deguchi and
Shohei Abe and
Masayasu Suzuki and
Kenichiro Anjo and
Toru Awashima and
Hideharu Amano},
editor = {Uwe Brinkschulte and
J{\"{u}}rgen Becker and
Dietmar Fey and
Christian Hochberger and
Thomas Martinetz and
Christian M{\"{u}}ller{-}Schloer and
Hartmut Schmeck and
Theo Ungerer and
Rolf P. W{\"{u}}rtz},
title = {Implementing core tasks of {JPEG2000} Encoder on the Dynamically Reconfigurable
Processor},
booktitle = {18th International Conference on Architecture of Computing Systems,
Workshops, Innsbruck, Austria, March 2005},
pages = {12--18},
publisher = {{VDE} Verlag},
year = {2005},
timestamp = {Fri, 19 Jul 2019 13:02:47 +0200},
biburl = {https://dblp.org/rec/conf/arcs/DeguchiASAAA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/AmanoAHDS05,
author = {Hideharu Amano and
Shohei Abe and
Yohei Hasegawa and
Katsuaki Deguchi and
Masayasu Suzuki},
title = {Performance and Cost Analysis of Time-Multiplexed Execution on the
Dynamically Reconfigurable Processor},
booktitle = {13th {IEEE} Symposium on Field-Programmable Custom Computing Machines
{(FCCM} 2005), 17-20 April 2005, Napa, CA, USA, Proceedings},
pages = {315--316},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/FCCM.2005.52},
doi = {10.1109/FCCM.2005.52},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/AmanoAHDS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HasegawaADSA05,
author = {Yohei Hasegawa and
Shohei Abe and
Katsuaki Deguchi and
Masayasu Suzuki and
Hideharu Amano},
editor = {Herman Schmit and
Steven J. E. Wilton},
title = {Time-multiplexed execution on the dynamically reconfigurable processor:
a performance/cost evaluation},
booktitle = {Proceedings of the {ACM/SIGDA} 13th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2005, Monterey, California, USA,
February 20-22, 2005},
pages = {265},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1046192.1046234},
doi = {10.1145/1046192.1046234},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/HasegawaADSA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/AmanoADH05,
author = {Hideharu Amano and
Shohei Abe and
Katsuaki Deguchi and
Yohei Hasegawa},
editor = {Tero Rissa and
Steven J. E. Wilton and
Philip Heng Wai Leong},
title = {An {I/O} mechanism on a Dynamically Reconfigurable Processor - Which
should be moved: Data or Configuration?},
booktitle = {Proceedings of the 2005 International Conference on Field Programmable
Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005},
pages = {347--352},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/FPL.2005.1515746},
doi = {10.1109/FPL.2005.1515746},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/AmanoADH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/OsanaIFYFHSIKA05,
author = {Yasunori Osana and
Yow Iwaoka and
Tomonori Fukushima and
Masato Yoshimi and
Akira Funahashi and
Noriko Hiroi and
Yuichiro Shibata and
Naoki Iwanaga and
Hiroaki Kitano and
Hideharu Amano},
editor = {Tero Rissa and
Steven J. E. Wilton and
Philip Heng Wai Leong},
title = {A Framework for ODE-Based Multimodel Biochemical Simulations on an
{FPGA}},
booktitle = {Proceedings of the 2005 International Conference on Field Programmable
Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005},
pages = {574--577},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/FPL.2005.1515788},
doi = {10.1109/FPL.2005.1515788},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/OsanaIFYFHSIKA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/IwanagaSYOIFAFHKO05,
author = {Naoki Iwanaga and
Yuichiro Shibata and
Masato Yoshimi and
Yasunori Osana and
Yow Iwaoka and
Tomonori Fukushima and
Hideharu Amano and
Akira Funahashi and
Noriko Hiroi and
Hiroaki Kitano and
Kiyoshi Oguri},
editor = {Tero Rissa and
Steven J. E. Wilton and
Philip Heng Wai Leong},
title = {Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel
Biochemical Simulation on an {FPGA}},
booktitle = {Proceedings of the 2005 International Conference on Field Programmable
Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005},
pages = {666--669},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/FPL.2005.1515809},
doi = {10.1109/FPL.2005.1515809},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/IwanagaSYOIFAFHKO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/TunbunhengSA05,
author = {Vasutan Tunbunheng and
Masayasu Suzuki and
Hideharu Amano},
editor = {Gordon J. Brebner and
Samarjit Chakraborty and
Weng{-}Fai Wong},
title = {RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for
Coarse Grain Reconfigurable Devices},
booktitle = {Proceedings of the 2005 {IEEE} International Conference on Field-Programmable
Technology, {FPT} 2005, 11-14 December 2005, Singapore},
pages = {129--136},
publisher = {{IEEE}},
year = {2005},
timestamp = {Tue, 19 Jun 2018 20:15:46 +0200},
biburl = {https://dblp.org/rec/conf/fpt/TunbunhengSA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/HasegawaAMAAA05,
author = {Yohei Hasegawa and
Shohei Abe and
Hiroki Matsutani and
Hideharu Amano and
Kenichiro Anjo and
Toru Awashima},
editor = {Gordon J. Brebner and
Samarjit Chakraborty and
Weng{-}Fai Wong},
title = {An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable
Processor},
booktitle = {Proceedings of the 2005 {IEEE} International Conference on Field-Programmable
Technology, {FPT} 2005, 11-14 December 2005, Singapore},
pages = {163--170},
publisher = {{IEEE}},
year = {2005},
timestamp = {Wed, 22 Feb 2006 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/HasegawaAMAAA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/YoshimiOIFHSIKA05,
author = {Masato Yoshimi and
Yasunori Osana and
Yow Iwaoka and
Akira Funahashi and
Noriko Hiroi and
Yuichiro Shibata and
Naoki Iwanaga and
Hiroaki Kitano and
Hideharu Amano},
editor = {Gordon J. Brebner and
Samarjit Chakraborty and
Weng{-}Fai Wong},
title = {The Design of Scalable Stochastic Biochemical Simulator on {FPGA}},
booktitle = {Proceedings of the 2005 {IEEE} International Conference on Field-Programmable
Technology, {FPT} 2005, 11-14 December 2005, Singapore},
pages = {339--340},
publisher = {{IEEE}},
year = {2005},
timestamp = {Wed, 22 Feb 2006 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/YoshimiOIFHSIKA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/OtsukaKJA05,
author = {Tomohiro Otsuka and
Michihiro Koibuchi and
Akiya Jouraku and
Hideharu Amano},
title = {VLAN-Based Minimal Paths in {PC} Cluster with Ethernet on Mesh and
Torus},
booktitle = {34th International Conference on Parallel Processing {(ICPP} 2005),
14-17 June 2005, Oslo, Norway},
pages = {567--576},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICPP.2005.79},
doi = {10.1109/ICPP.2005.79},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpp/OtsukaKJA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icppw/MatsutaniKYJA05,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Yutaka Yamada and
Akiya Jouraku and
Hideharu Amano},
title = {Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips},
booktitle = {34th International Conference on Parallel Processing Workshops {(ICPP}
2005 Workshops), 14-17 June 2005, Oslo, Norway},
pages = {273--280},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICPPW.2005.59},
doi = {10.1109/ICPPW.2005.59},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icppw/MatsutaniKYJA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/OsanaFYISKFHA05,
author = {Yasunori Osana and
Tomonori Fukushima and
Masato Yoshimi and
Yow Iwaoka and
Yuichiro Shibata and
Hiroaki Kitano and
Akira Funahashi and
Noriko Hiroi and
Hideharu Amano},
title = {An FPGA-Based, Multi-model Simulation Method for Biochemical Systems},
booktitle = {19th International Parallel and Distributed Processing Symposium {(IPDPS}
2005), {CD-ROM} / Abstracts Proceedings, 4-8 April 2005, Denver, CO,
{USA}},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/IPDPS.2005.103},
doi = {10.1109/IPDPS.2005.103},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ipps/OsanaFYISKFHA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iros/KurotakiSNOA05,
author = {Shunsuke Kurotaki and
Noriaki Suzuki and
Kazuhiro Nakadai and
Hiroshi G. Okuno and
Hideharu Amano},
title = {Implementation of active direction-pass filter on dynamically reconfigurable
processor},
booktitle = {2005 {IEEE/RSJ} International Conference on Intelligent Robots and
Systems, Edmonton, Alberta, Canada, August 2-6, 2005},
pages = {3175--3180},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/IROS.2005.1545033},
doi = {10.1109/IROS.2005.1545033},
timestamp = {Wed, 16 Oct 2019 14:14:51 +0200},
biburl = {https://dblp.org/rec/conf/iros/KurotakiSNOA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ishpc/MiyabeKHMITNA05,
author = {Yasuo Miyabe and
Akira Kitamura and
Yoshihiro Hamada and
Tomotaka Miyashiro and
Tetsu Izawa and
Noboru Tanabe and
Hironori Nakajo and
Hideharu Amano},
editor = {Jes{\'{u}}s Labarta and
Kazuki Joe and
Toshinori Sato},
title = {Implementation and Evaluation of the Mechanisms for Low Latency Communication
on DIMMnet-2},
booktitle = {High-Performance Computing - 6th International Symposium, {ISHPC}
2005, Nara, Japan, September 7-9, 2005, First International Workshop
on Advanced Low Power Systems, {ALPS} 2006, Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {4759},
pages = {211--218},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/978-3-540-77704-5\_18},
doi = {10.1007/978-3-540-77704-5\_18},
timestamp = {Tue, 14 May 2019 10:00:49 +0200},
biburl = {https://dblp.org/rec/conf/ishpc/MiyabeKHMITNA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdcat/KitamuraMIMWOAHTN05,
author = {Akira Kitamura and
Yasuo Miyabe and
Tetsu Izawa and
Tomotaka Miyashiro and
Konosuke Watanabe and
Tomohiro Otsuka and
Hideharu Amano and
Yoshihiro Hamada and
Noboru Tanabe and
Hironori Nakajo},
title = {Evaluation of Network Interface Controller on DIMMnet-2 Prototype
Board},
booktitle = {Sixth International Conference on Parallel and Distributed Computing,
Applications and Technologies {(PDCAT} 2005), 5-8 December 2005, Dalian,
China},
pages = {778--780},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/PDCAT.2005.136},
doi = {10.1109/PDCAT.2005.136},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/pdcat/KitamuraMIMWOAHTN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdpta/HanawaMTA05,
author = {Toshihiro Hanawa and
Toshiya Minai and
Yasuki Tanabe and
Hideharu Amano},
editor = {Hamid R. Arabnia},
title = {Implementation of ISIS-SimpleScalar},
booktitle = {Proceedings of the International Conference on Parallel and Distributed
Processing Techniques and Applications, {PDPTA} 2005, Las Vegas, Nevada,
USA, June 27-30, 2005, Volume 1},
pages = {117--123},
publisher = {{CSREA} Press},
year = {2005},
timestamp = {Wed, 25 Jan 2006 09:49:27 +0100},
biburl = {https://dblp.org/rec/conf/pdpta/HanawaMTA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdpta/HamadaNKTAN05,
author = {Yoshihiro Hamada and
Hiroaki Nishi and
Akira Kitamura and
Noboru Tanabe and
Hideharu Amano and
Hironori Nakajo},
editor = {Hamid R. Arabnia},
title = {A Packet Forwarding Layer for DIMMnet and its Hardware Implementation},
booktitle = {Proceedings of the International Conference on Parallel and Distributed
Processing Techniques and Applications, {PDPTA} 2005, Las Vegas, Nevada,
USA, June 27-30, 2005, Volume 2},
pages = {461--467},
publisher = {{CSREA} Press},
year = {2005},
timestamp = {Wed, 25 Jan 2006 09:50:17 +0100},
biburl = {https://dblp.org/rec/conf/pdpta/HamadaNKTAN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdpta/MatsutaniKA05,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
editor = {Hamid R. Arabnia},
title = {Destination Bundle: {A} Routing Table Reduction Technique for Distributed
Routing on Dependable Networks-on-Chips},
booktitle = {Proceedings of the International Conference on Parallel and Distributed
Processing Techniques and Applications, {PDPTA} 2005, Las Vegas, Nevada,
USA, June 27-30, 2005, Volume 3},
pages = {1343--1349},
publisher = {{CSREA} Press},
year = {2005},
timestamp = {Wed, 25 Jan 2006 09:52:18 +0100},
biburl = {https://dblp.org/rec/conf/pdpta/MatsutaniKA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/OsanaFYA04,
author = {Yasunori Osana and
Tomonori Fukushima and
Masato Yoshimi and
Hideharu Amano},
title = {An FPGA-Based Acceleration Method for Metabolic Simulation},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {87-D},
number = {8},
pages = {2029--2037},
year = {2004},
url = {http://search.ieice.org/bin/summary.php?id=e87-d\_8\_2029},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/OsanaFYA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ISCApdcs/SumiyoshiMTA04,
author = {Masato Sumiyoshi and
Takashi Midorikawa and
Yasuki Tanabe and
Hideharu Amano},
editor = {David A. Bader and
Ashfaq A. Khokhar},
title = {Design and Evaluation of a Switch Architecture for Multistage Interconnection
Network with Temporary Directory},
booktitle = {Proceedings of the {ISCA} 17th International Conference on Parallel
and Distributed Computing Systems, September 15-17, 2004, The Canterbury
Hotel, San Francisco, California, {USA}},
pages = {296--301},
publisher = {{ISCA}},
year = {2004},
timestamp = {Mon, 09 Aug 2021 16:35:42 +0200},
biburl = {https://dblp.org/rec/conf/ISCApdcs/SumiyoshiMTA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/OsanaFA04,
author = {Yasunori Osana and
Tomonori Fukushima and
Hideharu Amano},
editor = {Masaharu Imai},
title = {ReCSiP: a reconfigurable cell simulation platform: accelerating biological
applications with {FPGA}},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {731--733},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.172},
doi = {10.1109/ASPDAC.2004.172},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/OsanaFA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KawamuraA04,
author = {Masahiko Kawamura and
Hideharu Amano},
editor = {Masaharu Imai},
title = {Future reconfigurable computing system},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {798},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.105},
doi = {10.1109/ASPDAC.2004.105},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/KawamuraA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/euc/YamadaAKJAN04,
author = {Yutaka Yamada and
Hideharu Amano and
Michihiro Koibuchi and
Akiya Jouraku and
Kenichiro Anjo and
Katsunobu Nishimura},
editor = {Laurence Tianruo Yang and
Minyi Guo and
Guang R. Gao and
Niraj K. Jha},
title = {Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable
Processor Array},
booktitle = {Embedded and Ubiquitous Computing, International Conference {EUC}
2004, Aizu-Wakamatsu City, Japan, August 25-27, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3207},
pages = {301--311},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30121-9\_29},
doi = {10.1007/978-3-540-30121-9\_29},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/euc/YamadaAKJAN04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/SuzukiKSKYDHAAMWTA04,
author = {Noriaki Suzuki and
Shunsuke Kurotaki and
Masayasu Suzuki and
Naoto Kaneko and
Yutaka Yamada and
Katsuaki Deguchi and
Yohei Hasegawa and
Hideharu Amano and
Kenichiro Anjo and
Masato Motomura and
Kazutoshi Wakabayashi and
Takeo Toi and
Toru Awashima},
title = {Implementing and Evaluating Stream Applications on the Dynamically
Reconfigurable Processor},
booktitle = {12th {IEEE} Symposium on Field-Programmable Custom Computing Machines
{(FCCM} 2004), 20-23 April 2004, Napa, CA, USA, Proceedings},
pages = {328--329},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/FCCM.2004.42},
doi = {10.1109/FCCM.2004.42},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/SuzukiKSKYDHAAMWTA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/YoshimiOFA04,
author = {Masato Yoshimi and
Yasunori Osana and
Tomonori Fukushima and
Hideharu Amano},
editor = {J{\"{u}}rgen Becker and
Marco Platzner and
Serge Vernalde},
title = {Stochastic Simulation for Biochemical Reactions on {FPGA}},
booktitle = {Field Programmable Logic and Application, 14th International Conference
, {FPL} 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3203},
pages = {105--114},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30117-2\_13},
doi = {10.1007/978-3-540-30117-2\_13},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/YoshimiOFA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/AmanoIKFS04,
author = {Hideharu Amano and
Takeshi Inuo and
Hirokazu Kami and
Taro Fujii and
Masayasu Suzuki},
editor = {J{\"{u}}rgen Becker and
Marco Platzner and
Serge Vernalde},
title = {Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor
- An Approach to Tough Cases},
booktitle = {Field Programmable Logic and Application, 14th International Conference
, {FPL} 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3203},
pages = {464--473},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30117-2\_48},
doi = {10.1007/978-3-540-30117-2\_48},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/AmanoIKFS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/SuzukiHYKDAAMWTA04,
author = {Masayasu Suzuki and
Yohei Hasegawa and
Yutaka Yamada and
Naoto Kaneko and
Katsuaki Deguchi and
Hideharu Amano and
Kenichiro Anjo and
Masato Motomura and
Kazutoshi Wakabayashi and
Takao Toi and
Toru Awashima},
editor = {Oliver Diessel and
John Williams},
title = {Stream applications on the dynamically reconfigurable processor},
booktitle = {Proceedings of the 2004 {IEEE} International Conference on Field-Programmable
Technology, Brisbane, Australia, December 6-8, 2004},
pages = {137--144},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/FPT.2004.1393261},
doi = {10.1109/FPT.2004.1393261},
timestamp = {Fri, 22 Nov 2019 15:44:53 +0100},
biburl = {https://dblp.org/rec/conf/fpt/SuzukiHYKDAAMWTA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/AnjoYKJA04,
author = {Kenichiro Anjo and
Yutaka Yamada and
Michihiro Koibuchi and
Akiya Jouraku and
Hideharu Amano},
title = {{BLACK-BUS:} {A} New Data-Transfer Technique Using Local Address on
Networks-on-Chips},
booktitle = {18th International Parallel and Distributed Processing Symposium {(IPDPS}
2004), {CD-ROM} / Abstracts Proceedings, 26-30 April 2004, Santa Fe,
New Mexico, {USA}},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/IPDPS.2004.1302911},
doi = {10.1109/IPDPS.2004.1302911},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/AnjoYKJA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/parelec/TanabeNHNDA04,
author = {Noboru Tanabe and
Hironori Nakajo and
Hirotaka Hakozaki and
Masasige Nakatake and
Yasunori Dohi and
Hideharu Amano},
title = {A New Memory Module for Memory Intensive Applications},
booktitle = {2004 International Conference on Parallel Computing in Electrical
Engineering {(PARELEC} 2004), 7-10 September 2004, Dresden, Germany},
pages = {123--128},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/PCEE.2004.5},
doi = {10.1109/PCEE.2004.5},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/parelec/TanabeNHNDA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/appinf/OtsukaWTHYNKA03,
author = {Tomohiro Otsuka and
Konosuke Watanabe and
Junichiro Tsuchiya and
Hiroshi Harada and
Junji Yamamoto and
Hiroaki Nishi and
Tomohiro Kudoh and
Hideharu Amano},
editor = {M. H. Hamza},
title = {Performance Evaluation of a Prototype of RHiNET-2: {A} Network-based
Distributed Parallel Computing System},
booktitle = {The 21st {IASTED} International Multi-Conference on Applied Informatics
{(AI} 2003), February 10-13, 2003, Innsbruck, Austria},
pages = {738--743},
publisher = {{IASTED/ACTA} Press},
year = {2003},
timestamp = {Tue, 15 Jul 2003 16:03:54 +0200},
biburl = {https://dblp.org/rec/conf/appinf/OtsukaWTHYNKA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/YasufukuOIA03,
author = {Kenta Yasufuku and
Riku Ogawa and
Keisuke Iwai and
Hideharu Amano},
editor = {Hiroto Yasuura},
title = {{MAPLE} chip: a processing element for a static scheduling centric
multiprocessor},
booktitle = {Proceedings of the 2003 Asia and South Pacific Design Automation Conference,
{ASP-DAC} '03, Kitakyushu, Japan, January 21-24, 2003},
pages = {575--576},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/1119772.1119898},
doi = {10.1145/1119772.1119898},
timestamp = {Thu, 11 Mar 2021 17:04:51 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/YasufukuOIA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ccgrid/WatanabeOTAHYNK03,
author = {Konosuke Watanabe and
Tomohiro Otsuka and
Junichiro Tsuchiya and
Hideharu Amano and
Hiroshi Harada and
Junji Yamamoto and
Hiroaki Nishi and
Tomohiro Kudoh},
title = {Performance Evaluation of RHiNET-2/NI: {A} Network Interface for Distributed
Parallel Computing Systems},
booktitle = {3rd {IEEE} International Symposium on Cluster Computing and the Grid
(CCGrid 2003), 12-15 May 2003, Tokyo, Japan},
pages = {318--325},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/CCGRID.2003.1199383},
doi = {10.1109/CCGRID.2003.1199383},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ccgrid/WatanabeOTAHYNK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cluster/KoibuchiWKJA03,
author = {Michihiro Koibuchi and
Konosuke Watanabe and
Kenichi Kono and
Akiya Jouraku and
Hideharu Amano},
title = {Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster},
booktitle = {2003 {IEEE} International Conference on Cluster Computing {(CLUSTER}
2003), 1-4 December 2003, Kowloon, Hong Kong, China},
pages = {395},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/CLUSTR.2003.1253339},
doi = {10.1109/CLUSTR.2003.1253339},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cluster/KoibuchiWKJA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/AmanoJA03,
author = {Hideharu Amano and
Akiya Jouraku and
Kenichiro Anjo},
editor = {Peter Y. K. Cheung and
George A. Constantinides and
Jos{\'{e}} T. de Sousa},
title = {A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable
Device},
booktitle = {Field Programmable Logic and Application, 13th International Conference,
{FPL} 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2778},
pages = {161--170},
publisher = {Springer},
year = {2003},
url = {https://doi.org/10.1007/978-3-540-45234-8\_17},
doi = {10.1007/978-3-540-45234-8\_17},
timestamp = {Tue, 07 May 2024 20:11:13 +0200},
biburl = {https://dblp.org/rec/conf/fpl/AmanoJA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KitaokaAA03,
author = {Toshiro Kitaoka and
Hideharu Amano and
Kenichiro Anjo},
editor = {Peter Y. K. Cheung and
George A. Constantinides and
Jos{\'{e}} T. de Sousa},
title = {Reducing the Configuration Loading Time of a Coarse Grain Multicontext
Reconfigurable Device},
booktitle = {Field Programmable Logic and Application, 13th International Conference,
{FPL} 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2778},
pages = {171--180},
publisher = {Springer},
year = {2003},
url = {https://doi.org/10.1007/978-3-540-45234-8\_18},
doi = {10.1007/978-3-540-45234-8\_18},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/KitaokaAA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/OsanaFA03,
author = {Yasunori Osana and
Tomonori Fukushima and
Hideharu Amano},
editor = {Peter Y. K. Cheung and
George A. Constantinides and
Jos{\'{e}} T. de Sousa},
title = {Implementation of ReCSiP: {A} ReConfigurable Cell SImulation Platform},
booktitle = {Field Programmable Logic and Application, 13th International Conference,
{FPL} 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2778},
pages = {766--775},
publisher = {Springer},
year = {2003},
url = {https://doi.org/10.1007/978-3-540-45234-8\_74},
doi = {10.1007/978-3-540-45234-8\_74},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/OsanaFA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/AdachiITA03,
author = {Yoshinori Adachi and
Kenichiro Ishikawa and
Satoshi Tsutsumi and
Hideharu Amano},
title = {An implementation of the Rijndael on Async-WASMII},
booktitle = {Proceedings of the 2003 {IEEE} International Conference on Field-Programmable
Technology, Tokyo, Japan, {FPT} 2003, December 15-17, 2003},
pages = {44--51},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/FPT.2003.1275730},
doi = {10.1109/FPT.2003.1275730},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/AdachiITA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/KoibuchiJWA03,
author = {Michihiro Koibuchi and
Akiya Jouraku and
Konosuke Watanabe and
Hideharu Amano},
title = {Descending Layers Routing: {A} Deadlock-Free Deterministic Routing
using Virtual Channels in System Area Networks with Irregular Topologies},
booktitle = {32nd International Conference on Parallel Processing {(ICPP} 2003),
6-9 October 2003, Kaohsiung, Taiwan},
pages = {527},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ICPP.2003.1240620},
doi = {10.1109/ICPP.2003.1240620},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpp/KoibuchiJWA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdpta/TanabeMSSHA03,
author = {Yasuki Tanabe and
Takashi Midorikawa and
Daisuke Shiraishi and
Masayoshi Shigeno and
Toshihiro Hanawa and
Hideharu Amano},
editor = {Hamid R. Arabnia and
Youngsong Mun},
title = {Performance Evaluation of 3-Dimensional {MIN} with Cache Consistency
Maintenance Mechanism},
booktitle = {Proceedings of the International Conference on Parallel and Distributed
Processing Techniques and Applications, {PDPTA} '03, June 23 - 26,
2003, Las Vegas, Nevada, USA, Volume 3},
pages = {1148--1154},
publisher = {{CSREA} Press},
year = {2003},
timestamp = {Fri, 05 Dec 2003 09:24:17 +0100},
biburl = {https://dblp.org/rec/conf/pdpta/TanabeMSSHA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdpta/SuzukiA03,
author = {Noriaki Suzuki and
Hideharu Amano},
editor = {Hamid R. Arabnia and
Youngsong Mun},
title = {Performance Evaluation of Instruction Set Architecture of MBP-Light:
{A} Distributed Memory Controller for a Large Scale Multiprocessor},
booktitle = {Proceedings of the International Conference on Parallel and Distributed
Processing Techniques and Applications, {PDPTA} '03, June 23 - 26,
2003, Las Vegas, Nevada, USA, Volume 3},
pages = {1155--1164},
publisher = {{CSREA} Press},
year = {2003},
timestamp = {Wed, 08 Oct 2003 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/pdpta/SuzukiA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ishpc/2003,
editor = {Alexander V. Veidenbaum and
Kazuki Joe and
Hideharu Amano and
Hideo Aiso},
title = {High Performance Computing, 5th International Symposium, {ISHPC} 2003,
Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2858},
publisher = {Springer},
year = {2003},
url = {https://doi.org/10.1007/b14207},
doi = {10.1007/B14207},
isbn = {3-540-20359-1},
timestamp = {Tue, 14 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ishpc/2003.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cluster/TanabeYNKHNA02,
author = {Noboru Tanabe and
Junji Yamamoto and
Hiroaki Nishi and
Tomohiro Kudoh and
Yoshihiro Hamada and
Hironori Nakajo and
Hideharu Amano},
title = {Low Latency High Bandwidth Message Transfer Mechanisms for a Network
Interface Plugged into a Memory Slot},
journal = {Clust. Comput.},
volume = {5},
number = {1},
pages = {7--17},
year = {2002},
url = {https://doi.org/10.1023/A:1012732403321},
doi = {10.1023/A:1012732403321},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cluster/TanabeYNKHNA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KanekoA02,
author = {Naoto Kaneko and
Hideharu Amano},
editor = {Manfred Glesner and
Peter Zipf and
Michel Renovell},
title = {A General Hardware Design Model for Multicontext FPGAs},
booktitle = {Field-Programmable Logic and Applications, Reconfigurable Computing
Is Going Mainstream, 12th International Conference, {FPL} 2002, Montpellier,
France, September 2-4, 2002, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2438},
pages = {1037--1047},
publisher = {Springer},
year = {2002},
url = {https://doi.org/10.1007/3-540-46117-5\_106},
doi = {10.1007/3-540-46117-5\_106},
timestamp = {Sat, 30 Sep 2023 09:41:27 +0200},
biburl = {https://dblp.org/rec/conf/fpl/KanekoA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/IzuYTWA02,
author = {Naoyuki Izu and
Tomonori Yokoyama and
Junichiro Tsuchiya and
Konosuke Watanabe and
Hideharu Amano},
editor = {Manfred Glesner and
Peter Zipf and
Michel Renovell},
title = {RHiNET/NI: {A} Reconfigurable Network Interface for Cluster Computing},
booktitle = {Field-Programmable Logic and Applications, Reconfigurable Computing
Is Going Mainstream, 12th International Conference, {FPL} 2002, Montpellier,
France, September 2-4, 2002, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2438},
pages = {1118--1121},
publisher = {Springer},
year = {2002},
url = {https://doi.org/10.1007/3-540-46117-5\_121},
doi = {10.1007/3-540-46117-5\_121},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/IzuYTWA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispan/JourakuKAF02,
author = {Akiya Jouraku and
Michihiro Koibuchi and
Hideharu Amano and
Akira Funahashi},
title = {Routing Algorithms Based on 2D Turn Model for Irregular Networks},
booktitle = {International Symposium on Parallel Architectures, Algorithms and
Networks, {ISPAN} 2002, May 22-24, 2002, Makati City, Metro Manila,
Philippines},
pages = {289--294},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ISPAN.2002.1004296},
doi = {10.1109/ISPAN.2002.1004296},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispan/JourakuKAF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/parelec/TanabeHNIYKA02,
author = {Noboru Tanabe and
Yoshihiro Hamada and
Hironori Nakajo and
Hideki Imashiro and
Junji Yamamoto and
Tomohiro Kudoh and
Hideharu Amano},
title = {Low Latency Communication on DIMMnet-1 Network Interface Plugged into
a {DIMM} Slot},
booktitle = {2002 International Conference on Parallel Computing in Electrical
Engineering {(PARELEC} 2002), 22-25 September 2002, Warsaw, Poland},
pages = {9--14},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/PCEE.2002.1115189},
doi = {10.1109/PCEE.2002.1115189},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/parelec/TanabeHNIYKA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdpta/KoibuchiJA02,
author = {Michihiro Koibuchi and
Akiya Jouraku and
Hideharu Amano},
editor = {Hamid R. Arabnia},
title = {The Impact of Path Selection Algorithm of Adaptive Routing for Implementing
Deterministic Routing},
booktitle = {Proceedings of the International Conference on Parallel and Distributed
Processing Techniques and Applications, {PDPTA} '02, June 24 - 27,
2002, Las Vegas, Nevada, USA, Volume 3},
pages = {1431--1437},
publisher = {{CSREA} Press},
year = {2002},
timestamp = {Fri, 05 Dec 2003 09:24:05 +0100},
biburl = {https://dblp.org/rec/conf/pdpta/KoibuchiJA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/NishiTKA01,
author = {Hiroaki Nishi and
Koji Tasho and
Tomohiro Kudoh and
Hideharu Amano},
title = {A network switch for supporting high-performance parallel processing
by computers distributed in local areas},
journal = {Syst. Comput. Jpn.},
volume = {32},
number = {14},
pages = {24--33},
year = {2001},
url = {https://doi.org/10.1002/scj.1089},
doi = {10.1002/SCJ.1089},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/NishiTKA01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/YangFJNAS01,
author = {Yulu Yang and
Akira Funahashi and
Akiya Jouraku and
Hiroaki Nishi and
Hideharu Amano and
Toshinori Sueyoshi},
title = {Recursive Diagonal Torus: An Interconnection Network for Massively
Parallel Computers},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {12},
number = {7},
pages = {701--715},
year = {2001},
url = {https://doi.org/10.1109/71.940745},
doi = {10.1109/71.940745},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/YangFJNAS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ISCApdcs/KoibuchiJFA01,
author = {Michihiro Koibuchi and
Akiya Jouraku and
Akira Funahashi and
Hideharu Amano},
editor = {Edwin Hsing{-}Mean Sha},
title = {{MMLRU} Selection Function: An Output Selection Function on Adaptive
Routing},
booktitle = {Proceedings of the {ISCA} 14th International Conference on Parallel
and Distributed Computing Systems, August 8-10, 2001, Richardson,
Texas, {USA}},
pages = {1--6},
publisher = {{ISCA}},
year = {2001},
timestamp = {Mon, 09 Aug 2021 16:35:46 +0200},
biburl = {https://dblp.org/rec/conf/ISCApdcs/KoibuchiJFA01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KawakamiSA01,
author = {Daisuke Kawakami and
Yuichiro Shibata and
Hideharu Amano},
editor = {Satoshi Goto},
title = {A prototype chip of multicontext {FPGA} with {DRAM} for virtual hardware},
booktitle = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation
Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
pages = {17--18},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/370155.370215},
doi = {10.1145/370155.370215},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KawakamiSA01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cata/FunahashiKJA01,
author = {Akira Funahashi and
Michihiro Koibuchi and
Akiya Jouraku and
Hideharu Amano},
editor = {C. C. Hung},
title = {The impact of output selection function on adaptive routing},
booktitle = {Proceedings of the {ISCA} 16th International Conference Computers
and Their Applications, March 28-30, 2001, Seattle, Washington, {USA}},
pages = {241--246},
publisher = {{ISCA}},
year = {2001},
timestamp = {Mon, 09 Aug 2021 16:27:33 +0200},
biburl = {https://dblp.org/rec/conf/cata/FunahashiKJA01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hoti/NishimuraKNYUHFSATA01,
author = {Shinji Nishimura and
Tomohiro Kudoh and
Hiroaki Nishi and
Junji Yamamoto and
Ryuichiro Ueno and
Katsuyoshi Harasawa and
Shuji Fukuda and
Yasutaka Shikichi and
Shigeto Akutsu and
Koji Tasho and
Hideharu Amano},
title = {RHiNET-3/SW: an 80-Gbit/s high-speed network switch for distributed
parallel computing},
booktitle = {The Ninth Symposium on High Performance Interconnects, {HOTI} '01,
Stanford, CA, USA, August 22-24, 2001},
pages = {119--123},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/HIS.2001.946703},
doi = {10.1109/HIS.2001.946703},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hoti/NishimuraKNYUHFSATA01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/KoibuchiFJA01,
author = {Michihiro Koibuchi and
Akira Funahashi and
Akiya Jouraku and
Hideharu Amano},
editor = {Lionel M. Ni and
Mateo Valero},
title = {L-Turn Routing: An Adaptive Routing in Irregular Networks},
booktitle = {Proceedings of the 2001 International Conference on Parallel Processing,
{ICPP} 2002, 3-7 September 2001, Valencia, Spain},
pages = {383--392},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICPP.2001.952084},
doi = {10.1109/ICPP.2001.952084},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpp/KoibuchiFJA01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ngc/NishimuraHMAKNA00,
author = {Shinji Nishimura and
Katsuyoshi Harasawa and
N. Matsudaira and
Shigeto Akutsu and
Tomohiro Kudoh and
Hiroaki Nishi and
Hideharu Amano},
title = {RHiNET-2/SW a Hight-throughput, Compact Network-switch Using 8.8-Gbit/s
Optical Interconnection},
journal = {New Gener. Comput.},
volume = {18},
number = {2},
pages = {187--197},
year = {2000},
url = {https://doi.org/10.1007/BF03037597},
doi = {10.1007/BF03037597},
timestamp = {Thu, 14 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ngc/NishimuraHMAKNA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KawaguchiSA00,
author = {Takahiro Kawaguchi and
Takayuki Suzuki and
Hideharu Amano},
title = {A floating point arithmetic unit for a static scheduling and compiler
oriented multiprocessor system},
booktitle = {Proceedings of {ASP-DAC} 2000, Asia and South Pacific Design Automation
Conference 2000, Yokohama, Japan},
pages = {31--32},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/368434.368493},
doi = {10.1145/368434.368493},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/KawaguchiSA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cluster/TanabeYNKHNA00,
author = {Noboru Tanabe and
Junji Yamamoto and
Hiroaki Nishi and
Tomohiro Kudoh and
Yoshihiro Hamada and
Hironori Nakajo and
Hideharu Amano},
title = {MEMOnet : Network interface plugged into a memory slot},
booktitle = {2000 {IEEE} International Conference on Cluster Computing {(CLUSTER}
2000), November 28th - December 1st, 2000, Technische Universit{\"{a}}t
Chemnitz, Saxony, Germany},
pages = {17--16},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/CLUSTR.2000.888988},
doi = {10.1109/CLUSTR.2000.888988},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cluster/TanabeYNKHNA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/YamamotoSKA00,
author = {Ou Yamamoto and
Yuichiro Shibata and
Hitoshi Kurosawa and
Hideharu Amano},
title = {A Reconfigurable Stochastic Model Simulator for Analysis of Parallel
Systems},
booktitle = {8th {IEEE} Symposium on Field-Programmable Custom Computing Machines
{(FCCM} 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings},
pages = {291--294},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/FPGA.2000.903422},
doi = {10.1109/FPGA.2000.903422},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/YamamotoSKA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/ShibataUAFFM00,
author = {Yuichiro Shibata and
Masaki Uno and
Hideharu Amano and
Koichiro Furuta and
Taro Fujii and
Masato Motomura},
title = {A Virtual Hardware System on a Dynamically Reconfigurable Logic Device},
booktitle = {8th {IEEE} Symposium on Field-Programmable Custom Computing Machines
{(FCCM} 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings},
pages = {295--296},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/FPGA.2000.903423},
doi = {10.1109/FPGA.2000.903423},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/ShibataUAFFM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/YamamotoSKA00,
author = {Ou Yamamoto and
Yuichiro Shibata and
Hitoshi Kurosawa and
Hideharu Amano},
editor = {Reiner W. Hartenstein and
Herbert Gr{\"{u}}nbacher},
title = {A Reconfigurable Stochastic Model Simulator for Analysis of Parallel
Systems},
booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable
Computing, 10th International Workshop, {FPL} 2000, Villach, Austria,
August 27-30, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1896},
pages = {475--484},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-44614-1\_52},
doi = {10.1007/3-540-44614-1\_52},
timestamp = {Tue, 14 May 2019 10:00:48 +0200},
biburl = {https://dblp.org/rec/conf/fpl/YamamotoSKA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/AmanoSU00,
author = {Hideharu Amano and
Yuichiro Shibata and
Masaki Uno},
editor = {Reiner W. Hartenstein and
Herbert Gr{\"{u}}nbacher},
title = {Reconfigurable Systems: New Activities in Asia},
booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable
Computing, 10th International Workshop, {FPL} 2000, Villach, Austria,
August 27-30, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1896},
pages = {585--594},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-44614-1\_63},
doi = {10.1007/3-540-44614-1\_63},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/AmanoSU00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/TakayamaSIA00,
author = {Atsushi Takayama and
Yuichiro Shibata and
Keisuke Iwai and
Hideharu Amano},
editor = {Reiner W. Hartenstein and
Herbert Gr{\"{u}}nbacher},
title = {Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual
Hardware},
booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable
Computing, 10th International Workshop, {FPL} 2000, Villach, Austria,
August 27-30, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1896},
pages = {685--694},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-44614-1\_73},
doi = {10.1007/3-540-44614-1\_73},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/TakayamaSIA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpdc/NishiTYKA00,
author = {Hiroaki Nishi and
Koji Tasho and
Junji Yamamoto and
Tomohiro Kudoh and
Hideharu Amano},
title = {A Local Area System Network RHinet-1: {A} Network for High Performance
Parallel Computing},
booktitle = {Proceedings of the Ninth {IEEE} International Symposium on High Performance
Distributed Computing, HPDC'00, Pittsburgh, Pennsylvania, USA, August
1-4, 2000},
pages = {296--297},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/HPDC.2000.868665},
doi = {10.1109/HPDC.2000.868665},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hpdc/NishiTYKA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispan/HoritaW00,
author = {Masaki Wakabayashi and
Hideharu Amano},
title = {Environment for Multiprocessor Simulator Development},
booktitle = {5th International Symposium on Parallel Architectures, Algorithms,
and Networks {(I-SPAN} 2000), 7-10 December 2000, Dallas / Richardson,
TX, {USA}},
pages = {64--71},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ISPAN.2000.900263},
doi = {10.1109/ISPAN.2000.900263},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispan/HoritaW00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispan/TanabeYNKHNA00,
author = {Noboru Tanabe and
Junji Yamamoto and
Hiroaki Nishi and
Tomohiro Kudoh and
Yoshihiro Hamada and
Hironori Nakajo and
Hideharu Amano},
title = {On-the-fly Sending: {A} Low Latency High Bandwidth Message Transfer
Mechanism},
booktitle = {5th International Symposium on Parallel Architectures, Algorithms,
and Networks {(I-SPAN} 2000), 7-10 December 2000, Dallas / Richardson,
TX, {USA}},
pages = {186--194},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ISPAN.2000.900284},
doi = {10.1109/ISPAN.2000.900284},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ispan/TanabeYNKHNA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdpta/NakajoIKA00,
author = {Hironori Nakajo and
M. Ishii and
T. Kudo and
Hideharu Amano},
editor = {Hamid R. Arabnia},
title = {Coherence Protocol for Home Proxy Cache on RHiNET},
booktitle = {Proceedings of the International Conference on Parallel and Distributed
Processing Techniques and Applications, {PDPTA} 2000, June 24-29,
2000, Las Vegas, Nevada, {USA}},
publisher = {{CSREA} Press},
year = {2000},
timestamp = {Mon, 08 Dec 2003 16:35:08 +0100},
biburl = {https://dblp.org/rec/conf/pdpta/NakajoIKA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pc/YamamotoFKKHA99,
author = {Junji Yamamoto and
Takashi Fujiwara and
T. Komeda and
Takayuki Kamei and
Toshihiro Hanawa and
Hideharu Amano},
title = {Performance evaluation of {SNAIL:} {A} multiprocessor based on the
simple serial synchronized multistage interconnection network architecture},
journal = {Parallel Comput.},
volume = {25},
number = {9},
pages = {1081--1103},
year = {1999},
url = {https://doi.org/10.1016/S0167-8191(99)00038-1},
doi = {10.1016/S0167-8191(99)00038-1},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/pc/YamamotoFKKHA99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/appinf/WakabayashiIA99,
author = {Masaki Wakabayashi and
Keisuke Inoue and
Hideharu Amano},
editor = {M. H. Hamza},
title = {{ISIS:} Multiprocessor Simulator Library},
booktitle = {Proceedings of the 17th {IASTED} International Conference on Applied
Informatics, February 15-18, 1999, Innsbruck, Austria},
pages = {198--200},
publisher = {{IASTED/ACTA} Press},
year = {1999},
timestamp = {Thu, 31 Aug 2006 10:34:29 +0200},
biburl = {https://dblp.org/rec/conf/appinf/WakabayashiIA99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/appinf/DongKA99,
author = {Xiaoshe Dong and
Tomohiro Kudoh and
Hideharu Amano},
editor = {M. H. Hamza},
title = {A Routing Algorithm for {DS-WDM} Ring},
booktitle = {Proceedings of the 17th {IASTED} International Conference on Applied
Informatics, February 15-18, 1999, Innsbruck, Austria},
pages = {562--565},
publisher = {{IASTED/ACTA} Press},
year = {1999},
timestamp = {Thu, 31 Aug 2006 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/appinf/DongKA99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/appinf/KawaguchiFSIA99,
author = {Takahiro Kawaguchi and
Takashi Fujiwara and
Katsuto Sakamoto and
Keisuke Iwai and
Hideharu Amano},
editor = {M. H. Hamza},
title = {Floating Point Arithmetic Unit for the Custom Processor Maple},
booktitle = {Proceedings of the 17th {IASTED} International Conference on Applied
Informatics, February 15-18, 1999, Innsbruck, Austria},
pages = {578--580},
publisher = {{IASTED/ACTA} Press},
year = {1999},
timestamp = {Thu, 31 Aug 2006 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/appinf/KawaguchiFSIA99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icppw/TakayamaSIMHLA99,
author = {Atsushi Takayama and
Yuichiro Shibata and
Keisuke Iwai and
Hidenori Miyazaki and
Koichi Higure and
Xiao{-}ping Ling and
Hideharu Amano},
title = {Implementation and Evaluation of the Compiler for WASMII, a Virtual
Hardware System},
booktitle = {Proceedings of the 1999 International Conference on Parallel Processing
Workshops, {ICPPW} 1999, Wakamatsu, Japan, September 21-24, 1999},
pages = {346--351},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICPPW.1999.800084},
doi = {10.1109/ICPPW.1999.800084},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icppw/TakayamaSIMHLA99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icppw/ShibataLA99,
author = {Yuichiro Shibata and
Xiao{-}ping Ling and
Hideharu Amano},
title = {Internal Parallelization of Data-Driven Virtual Hardware},
booktitle = {Proceedings of the 1999 International Conference on Parallel Processing
Workshops, {ICPPW} 1999, Wakamatsu, Japan, September 21-24, 1999},
pages = {366--373},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICPPW.1999.800087},
doi = {10.1109/ICPPW.1999.800087},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icppw/ShibataLA99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispan/FanYFA99,
author = {Qin Fan and
Yulu Yang and
Akira Funahashi and
Hideharu Amano},
title = {A Torus Assignment for an Interconnection Network Recursive Diagonal
Torus},
booktitle = {1999 International Symposium on Parallel Architectures, Algorithms
and Networks {(ISPAN} '99), 23-25 June 1999, Fremantle, Australia},
pages = {74--79},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ISPAN.1999.778920},
doi = {10.1109/ISPAN.1999.778920},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispan/FanYFA99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mse/MorisawaKTA99,
author = {Fumiharu Morisawa and
Daisuke Kawakami and
Kensuke Tanaka and
Hideharu Amano},
title = {An Educational System of {LSI} Design with Free-Wares for {VDEC}},
booktitle = {{IEEE} International Conference on Microelectronic Systems Education,
{MSE} 1999, Arlington, Virginia, USA, July 19-21, 1999},
pages = {61--62},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MSE.1999.787038},
doi = {10.1109/MSE.1999.787038},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mse/MorisawaKTA99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ar/MiyajimaNAA98,
author = {Asami Miyajima and
Kazumasa Nukata and
Hideharu Amano and
Yuichiro Anzai},
title = {Design and implementation of reconfigurable sensing system for networked
robots},
journal = {Adv. Robotics},
volume = {13},
number = {3},
pages = {253--254},
year = {1998},
url = {https://doi.org/10.1163/156855399X00450},
doi = {10.1163/156855399X00450},
timestamp = {Sat, 25 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ar/MiyajimaNAA98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/YamamotoTA98,
author = {Ou Yamamoto and
Takuya Terasawa and
Hideharu Amano},
title = {An analysis of fairness and overhead in the arbitration protocol of
the {IEEE} Futurebus standard},
journal = {Syst. Comput. Jpn.},
volume = {29},
number = {13},
pages = {66--77},
year = {1998},
url = {https://doi.org/10.1002/(SICI)1520-684X(19981130)29:13\&\#60;66::AID-SCJ8\&\#62;3.0.CO;2-O},
doi = {10.1002/(SICI)1520-684X(19981130)29:13\&\#60;66::AID-SCJ8\&\#62;3.0.CO;2-O},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/YamamotoTA98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/MidorikawaKHA98,
author = {Takashi Midorikawa and
Takayuki Kamei and
Toshihiro Hanawa and
Hideharu Amano},
title = {The {MINC} (Multistage Interconnection Network with Cache Control
Mechanism) Chip},
booktitle = {Proceedings of the {ASP-DAC} '98, Asia and South Pacific Design Automation
Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13,
1998},
pages = {337--338},
publisher = {{IEEE}},
year = {1998},
url = {https://doi.org/10.1109/ASPDAC.1998.669494},
doi = {10.1109/ASPDAC.1998.669494},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/MidorikawaKHA98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/AmanoS98,
author = {Hideharu Amano and
Yuichiro Shibata},
title = {Reconfigurable Systems: Activities in Asia and South Pacific (Embedded
Tutorial)},
booktitle = {Proceedings of the {ASP-DAC} '98, Asia and South Pacific Design Automation
Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13,
1998},
pages = {453--457},
publisher = {{IEEE}},
year = {1998},
url = {https://doi.org/10.1109/ASPDAC.1998.669521},
doi = {10.1109/ASPDAC.1998.669521},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/AmanoS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/ShibataMLA98,
author = {Yuichiro Shibata and
Hidenori Miyazaki and
Xiao{-}ping Ling and
Hideharu Amano},
editor = {Jos{\'{e}} D. P. Rolim},
title = {{HOSMII:} {A} Virtual Hardware Integrated with {DRAM}},
booktitle = {Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held
in Conjunction with the 12th International Parallel Processing Symposium
and 9th Symposium on Parallel and Distributed Processing, Orlando,
Florida, USA, March 30 - April 3, 1998, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1388},
pages = {85--90},
publisher = {Springer},
year = {1998},
url = {https://doi.org/10.1007/3-540-64359-1\_678},
doi = {10.1007/3-540-64359-1\_678},
timestamp = {Sat, 03 Aug 2019 19:28:45 +0200},
biburl = {https://dblp.org/rec/conf/ipps/ShibataMLA98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/TerasawaIKA97,
author = {Takuya Terasawa and
Keisuke Inoue and
Hitoshi Kurosawa and
Hideharu Amano},
title = {A study on snoop cache systems for single-chip multiprocessors},
journal = {Syst. Comput. Jpn.},
volume = {28},
number = {2},
pages = {62--72},
year = {1997},
url = {https://doi.org/10.1002/(SICI)1520-684X(199702)28:2\&\#60;62::AID-SCJ7\&\#62;3.0.CO;2-P},
doi = {10.1002/(SICI)1520-684X(199702)28:2\&\#60;62::AID-SCJ7\&\#62;3.0.CO;2-P},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/TerasawaIKA97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/aspdac/KameiSA97,
author = {Takayuki Kamei and
Masashi Sasahara and
Hideharu Amano},
title = {An {LSI} implementation of the simple serial synchronized multistage
interconnection network},
booktitle = {Proceedings of the {ASP-DAC} '97 Asia and South Pacific Design Automation
Conference, Nippon Convention Center, Chiba, Japan, January 28-31,
1997},
pages = {673--674},
publisher = {{IEEE}},
year = {1997},
url = {https://doi.org/10.1109/ASPDAC.1997.600358},
doi = {10.1109/ASPDAC.1997.600358},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KameiSA97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/NishiANAK97,
author = {Hiroaki Nishi and
Hideharu Amano and
Katsunobu Nishimura and
Kenichiro Anjo and
Tomohiro Kudoh},
title = {The {RDT} network router chip},
booktitle = {Proceedings of the {ASP-DAC} '97 Asia and South Pacific Design Automation
Conference, Nippon Convention Center, Chiba, Japan, January 28-31,
1997},
pages = {675--676},
publisher = {{IEEE}},
year = {1997},
url = {https://doi.org/10.1109/ASPDAC.1997.600359},
doi = {10.1109/ASPDAC.1997.600359},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/NishiANAK97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/europar/KisukiWYIA97,
author = {Toru Kisuki and
Masaki Wakabayashi and
Junji Yamamoto and
Keisuke Inoue and
Hideharu Amano},
editor = {Christian Lengauer and
Martin Griebl and
Sergei Gorlatch},
title = {Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors},
booktitle = {Euro-Par '97 Parallel Processing, Third International Euro-Par Conference,
Passau, Germany, August 26-29, 1997, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1300},
pages = {793--797},
publisher = {Springer},
year = {1997},
url = {https://doi.org/10.1007/BFb0002815},
doi = {10.1007/BFB0002815},
timestamp = {Tue, 14 May 2019 10:00:46 +0200},
biburl = {https://dblp.org/rec/conf/europar/KisukiWYIA97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/NukataSAA97,
author = {Kazumasa Nukata and
Yuichiro Shibata and
Hideharu Amano and
Yuichiro Anzai},
editor = {Wayne Luk and
Peter Y. K. Cheung and
Manfred Glesner},
title = {A reconfigurable sensor-data processing system for personal robots},
booktitle = {Field-Programmable Logic and Applications, 7th International Workshop,
{FPL} '97, London, UK, September 1-3, 1997, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1304},
pages = {491--500},
publisher = {Springer},
year = {1997},
url = {https://doi.org/10.1007/3-540-63465-7\_255},
doi = {10.1007/3-540-63465-7\_255},
timestamp = {Tue, 14 May 2019 10:00:48 +0200},
biburl = {https://dblp.org/rec/conf/fpl/NukataSAA97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ishpc/FunahashiHAK97,
author = {Akira Funahashi and
Toshihiro Hanawa and
Hideharu Amano and
Tomohiro Kudoh},
editor = {Constantine D. Polychronopoulos and
Kazuki Joe and
Keijiro Araki and
Makoto Amamiya},
title = {Adaptive Routing on the Recursive Diagonal Torus},
booktitle = {High Performance Computing, International Symposium, ISHPC'97, Fukuoka,
Japan, November 4-6, 1997, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1336},
pages = {171--182},
publisher = {Springer},
year = {1997},
url = {https://doi.org/10.1007/BFb0024214},
doi = {10.1007/BFB0024214},
timestamp = {Tue, 14 May 2019 10:00:49 +0200},
biburl = {https://dblp.org/rec/conf/ishpc/FunahashiHAK97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/ispan/DongKA97,
author = {Xiaoshe Dong and
Tomohiro Kudoh and
Hideharu Amano},
title = {Wavelength Division Multiple Access Ring - Virtual Topology on a Simple
Ring Network},
booktitle = {1997 International Symposium on Parallel Architectures, Algorithms
and Networks {(ISPAN} '97), 18-20 December 1997, Taipei, Taiwan},
pages = {30--36},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ISPAN.1997.645049},
doi = {10.1109/ISPAN.1997.645049},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispan/DongKA97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/pdpta/LingSMAH97,
author = {Xiao{-}ping Ling and
Yuichiro Shibata and
Hidenori Miyazaki and
Hideharu Amano and
Koichi Higure},
editor = {Hamid R. Arabnia},
title = {Total System Image of the Reconfigurable Machine {WASMII}},
booktitle = {Proceedings of the International Conference on Parallel and Distributed
Processing Techniques and Applications, {PDPTA} 1997, June 30 - July
3, 1997, Las Vegas, Nevada, {USA}},
pages = {1092--1096},
publisher = {{CSREA} Press},
year = {1997},
timestamp = {Tue, 20 Apr 2004 14:47:02 +0200},
biburl = {https://dblp.org/rec/conf/pdpta/LingSMAH97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@article{DBLP:journals/scjapan/YangASS96,
author = {Yulu Yang and
Hideharu Amano and
Hidetomo Shibamura and
Toshinori Sueyoshi},
title = {Recursive Diagonal Torus {(RDT):} An Interconnection Network for the
Massively Parallel Computers},
journal = {Syst. Comput. Jpn.},
volume = {27},
number = {9},
pages = {43--54},
year = {1996},
url = {https://doi.org/10.1002/scj.4690270905},
doi = {10.1002/SCJ.4690270905},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/YangASS96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/fpl/ShibataLA96,
author = {Yuichiro Shibata and
Xiao{-}ping Ling and
Hideharu Amano},
editor = {Reiner W. Hartenstein and
Manfred Glesner},
title = {An Emulation System of the {WASMII:} {A} Data Driven Computer on a
Virtual Hardware},
booktitle = {Field-Programmable Logic, Smart Applications, New Paradigms and Compilers,
6th International Workshop on Field-Programmable Logic, {FPL} '96,
Darmstadt, Germany, September 23-25, 1996, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1142},
pages = {55--64},
publisher = {Springer},
year = {1996},
url = {https://doi.org/10.1007/3-540-61730-2\_6},
doi = {10.1007/3-540-61730-2\_6},
timestamp = {Tue, 14 May 2019 10:00:48 +0200},
biburl = {https://dblp.org/rec/conf/fpl/ShibataLA96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/fpl/InoueKOSTA96,
author = {Keisuke Inoue and
Toru Kisuki and
Michitaka Okuno and
Etsuko Shimizu and
Takuya Terasawa and
Hideharu Amano},
editor = {Reiner W. Hartenstein and
Manfred Glesner},
title = {{ATTEMPT-1:} {A} Reconfigurable Multiprocessor Testbed},
booktitle = {Field-Programmable Logic, Smart Applications, New Paradigms and Compilers,
6th International Workshop on Field-Programmable Logic, {FPL} '96,
Darmstadt, Germany, September 23-25, 1996, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1142},
pages = {200--209},
publisher = {Springer},
year = {1996},
url = {https://doi.org/10.1007/3-540-61730-2\_21},
doi = {10.1007/3-540-61730-2\_21},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/InoueKOSTA96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/spdp/HanawaFA96,
author = {Toshihiro Hanawa and
Takashi Fujiwara and
Hideharu Amano},
title = {Hot spot contention and message combining in the simple serial synchronized
multistage interconnection network},
booktitle = {Proceedings of the Eighth {IEEE} Symposium on Parallel and Distributed
Processing, {SPDP} 1996, New Orleans, Louisiana, USA, October 23-26,
1996},
pages = {298--305},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/SPDP.1996.570347},
doi = {10.1109/SPDP.1996.570347},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/spdp/HanawaFA96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijon/SuzukiAT95,
author = {Kyotaro Suzuki and
Hideharu Amano and
Yoshiyasu Takefuji},
title = {Neural network parallel computing for multi-layer channel routing
problems},
journal = {Neurocomputing},
volume = {8},
number = {2},
pages = {141--156},
year = {1995},
url = {https://doi.org/10.1016/0925-2312(94)00014-J},
doi = {10.1016/0925-2312(94)00014-J},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijon/SuzukiAT95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pc/TerasawaYKA95,
author = {Takuya Terasawa and
Ou Yamamoto and
Tomohiro Kudoh and
Hideharu Amano},
title = {A Performance Evaluation of the Multiprocessor Testbed {ATTEMPT-0}},
journal = {Parallel Comput.},
volume = {21},
number = {5},
pages = {701--730},
year = {1995},
url = {https://doi.org/10.1016/0167-8191(94)00111-M},
doi = {10.1016/0167-8191(94)00111-M},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/pc/TerasawaYKA95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/GayeHA95,
author = {Kalidou Gaye and
Toshihiro Hanawa and
Hideharu Amano},
title = {An analysis of the hot spot contention and message combining on the
simple serial synchronized-multistage interconnection network},
journal = {Syst. Comput. Jpn.},
volume = {26},
number = {9},
pages = {1--12},
year = {1995},
url = {https://doi.org/10.1002/scj.4690260901},
doi = {10.1002/SCJ.4690260901},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/GayeHA95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tjs/LingA95,
author = {Xiao{-}ping Ling and
Hideharu Amano},
title = {{WASMII:} An {MPLD} with data-driven control on a virtual hardware},
journal = {J. Supercomput.},
volume = {9},
number = {3},
pages = {253--276},
year = {1995},
url = {https://doi.org/10.1007/BF01212871},
doi = {10.1007/BF01212871},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tjs/LingA95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/KudohAMHYNYF95,
author = {Tomohiro Kudoh and
Hideharu Amano and
Takashi Matsumoto and
Kei Hiraki and
Yulu Yang and
Katsunobu Nishimura and
Koichi Yoshimura and
Yasuhito Fukushima},
editor = {Prithviraj Banerjee},
title = {Hierarchical Bit-Map Directory Schemes on the {RDT} Interconnection
Network for a Massively Parallel Processor {JUMP-1}},
booktitle = {Proceedings of the 1995 International Conference on Parallel Processing,
Urbana-Champain, Illinois, USA, August 14-18, 1995. Volume {I:} Architecture},
pages = {186--193},
publisher = {{CRC} Press},
year = {1995},
timestamp = {Fri, 16 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icpp/KudohAMHYNYF95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdpcs/YamamotoHYTYA95,
author = {Junji Yamamoto and
D. Hattori and
Jun{-}ichi Yamato and
T. Tokuyoshi and
Y. Yamaguchi and
Hideharu Amano},
editor = {M. H. Hamza},
title = {A Preprocessing System of the {EULASH:} An Environment for Efficient
use of Multiprocessors with Local Memory},
booktitle = {Proceedings of the Seventh {IASTED/ISMM} International Conference
on Parallel and Distributed Computing and Systems, Washington, D.C.,
USA, October 19-21, 1995},
pages = {68--71},
publisher = {{IASTED/ACTA} Press},
year = {1995},
timestamp = {Wed, 14 Jul 2004 15:48:48 +0200},
biburl = {https://dblp.org/rec/conf/pdpcs/YamamotoHYTYA95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ChenLA94,
author = {Xiao{-}yu Chen and
Xiao{-}ping Ling and
Hideharu Amano},
editor = {Reiner W. Hartenstein and
Michal Serv{\'{\i}}t},
title = {Software Environment for {WASMII:} a Data Driven Machine with a Virtual
Hardware},
booktitle = {Field-Programmable Logic, Architectures, Synthesis and Applications,
4th International Workshop on Field-Programmable Logic and Applications,
{FPL} '94, Prague, Czech Republic, September 7-9, 1994, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {849},
pages = {208--219},
publisher = {Springer},
year = {1994},
url = {https://doi.org/10.1007/3-540-58419-6\_91},
doi = {10.1007/3-540-58419-6\_91},
timestamp = {Tue, 14 May 2019 10:00:48 +0200},
biburl = {https://dblp.org/rec/conf/fpl/ChenLA94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/HanawaAF94,
author = {Toshihiro Hanawa and
Hideharu Amano and
Yoshifumi Fujikawa},
editor = {Dharma P. Agrawal},
title = {Multistage Interconnection Networks with Multiple Outlets},
booktitle = {Proceedings of the 1994 International Conference on Parallel Processing,
North Carolina State University, NC, USA, August 15-19, 1994. Volume
{I:} Architecture},
pages = {1--8},
publisher = {{CRC} Press},
year = {1994},
url = {https://doi.org/10.1109/ICPP.1994.133},
doi = {10.1109/ICPP.1994.133},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpp/HanawaAF94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/SasaharaTZGYOA94,
author = {Masashi Sasahara and
Jun Terada and
Luo Zhou and
Kalidou Gaye and
Jun{-}ichi Yamato and
Satoshi Ogura and
Hideharu Amano},
editor = {Dharma P. Agrawal},
title = {{SNAIL:} {A} Multiprocessor Based on the Simple Serial Synchronized
Multistage Interconnection Network Architecture},
booktitle = {Proceedings of the 1994 International Conference on Parallel Processing,
North Carolina State University, NC, USA, August 15-19, 1994. Volume
{I:} Architecture},
pages = {117--120},
publisher = {{CRC} Press},
year = {1994},
url = {https://doi.org/10.1109/ICPP.1994.182},
doi = {10.1109/ICPP.1994.182},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpp/SasaharaTZGYOA94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispan/YangA94,
author = {Yulu Yang and
Hideharu Amano},
title = {Message transfer algorithms on the recursive diagonal torus},
booktitle = {International Symposium on Parallel Architectures, Algorithms and
Networks, {ISPAN} 1994, Kanazawa, Japan, December 14-16, 1994},
pages = {310--317},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/ISPAN.1994.367185},
doi = {10.1109/ISPAN.1994.367185},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispan/YangA94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispan/HirakiAKSKNNMMM94,
author = {Kei Hiraki and
Hideharu Amano and
Morihiro Kuga and
Toshinori Sueyoshi and
Tomohiro Kudoh and
Hiroshi Nakashima and
Hironori Nakajo and
Hideo Matsuda and
Takashi Matsumoto and
Shin{-}ichiro Mori},
title = {Overview of the JUMP-1, an {MPP} prototype for general-purpose parallel
computations},
booktitle = {International Symposium on Parallel Architectures, Algorithms and
Networks, {ISPAN} 1994, Kanazawa, Japan, December 14-16, 1994},
pages = {427--434},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/ISPAN.1994.367136},
doi = {10.1109/ISPAN.1994.367136},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispan/HirakiAKSKNNMMM94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/KudohKAT93,
author = {Tomohiro Kudoh and
Tetsuro Kimura and
Hideharu Amano and
Takuya Terasawa},
title = {A query-based parallel logic simulation algorithm},
journal = {Syst. Comput. Jpn.},
volume = {24},
number = {2},
pages = {11--21},
year = {1993},
url = {https://doi.org/10.1002/scj.4690240202},
doi = {10.1002/SCJ.4690240202},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/KudohKAT93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/parle/LingA93,
author = {Xiao{-}ping Ling and
Hideharu Amano},
editor = {Arndt Bode and
Mike Reeve and
Gottfried Wolf},
title = {Performance evaluation of {WASMII:} a data driven computer on a virtual
hardware},
booktitle = {{PARLE} '93, Parallel Architectures and Languages Europe, 5th International
{PARLE} Conference, Munich, Germany, June 14-17, 1993, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {694},
pages = {610--621},
publisher = {Springer},
year = {1993},
url = {https://doi.org/10.1007/3-540-56891-3\_49},
doi = {10.1007/3-540-56891-3\_49},
timestamp = {Tue, 14 May 2019 10:00:52 +0200},
biburl = {https://dblp.org/rec/conf/parle/LingA93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/spdp/YangASS93,
author = {Yulu Yang and
Hideharu Amano and
Hidetomo Shibamura and
Toshinori Sueyoshi},
title = {Recursive Diagonal Torus: An Interconnection Network for Massively
Parallel Computers},
booktitle = {Proceedings of the Fifth {IEEE} Symposium on Parallel and Distributed
Processing, {SPDP} 1993, Dallas, Texas, USA, December 2-5, 1993},
pages = {591--595},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.org/10.1109/SPDP.1993.395481},
doi = {10.1109/SPDP.1993.395481},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/spdp/YangASS93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/KudohKAT92,
author = {Tomohiro Kudoh and
Tetsuro Kimura and
Hideharu Amano and
Takuya Terasawa},
editor = {Quentin F. Stout},
title = {A Parallel Logic Simulation Algorithm Based on Query},
booktitle = {Proceedings of the 1992 International Conference on Parallel Processing,
University of Michigan, An Arbor, Michigan, USA, August 17-21, 1992.
Volume {III:} Algorithms {\&} Applications},
pages = {262--266},
publisher = {{CRC} Press},
year = {1992},
timestamp = {Mon, 28 Jul 2014 17:06:01 +0200},
biburl = {https://dblp.org/rec/conf/icpp/KudohKAT92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ifip/AmanoZG92,
author = {Hideharu Amano and
Luo Zhou and
Kalidou Gaye},
editor = {Jan van Leeuwen},
title = {{SSS} (Simple Serial Synchronized)-MIN: {A} Novel Multi Stage Interconnection
Architecture for Multiprocessors},
booktitle = {Algorithms, Software, Architecture - Information Processing '92, Volume
1, Proceedings of the {IFIP} 12th World Computer Congress, Madrid,
Spain, 7-11 September 1992},
series = {{IFIP} Transactions},
volume = {{A-12}},
pages = {571--577},
publisher = {North-Holland},
year = {1992},
timestamp = {Wed, 14 Aug 2002 08:51:19 +0200},
biburl = {https://dblp.org/rec/conf/ifip/AmanoZG92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/BokuKAK91,
author = {Taisuke Boku and
Tomohiro Kudoh and
Hideharu Amano and
Tetsuro Kimura},
title = {{NCC:} {A} concurrent description language for scientific calculation
on multiprocessors},
journal = {Syst. Comput. Jpn.},
volume = {22},
number = {12},
pages = {1--10},
year = {1991},
url = {https://doi.org/10.1002/scj.4690221201},
doi = {10.1002/SCJ.4690221201},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/BokuKAK91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/AmanoG91,
author = {Hideharu Amano and
Kalidou Gaye},
title = {A Batcher Double Omega Network with Combining},
booktitle = {Proceedings of the International Conference on Parallel Processing,
{ICPP} '91, Austin, Texas, USA, August 1991. Volume {I:} Architecture/Hardware},
pages = {718--719},
publisher = {{CRC} Press},
year = {1991},
timestamp = {Mon, 28 Jul 2014 17:06:00 +0200},
biburl = {https://dblp.org/rec/conf/icpp/AmanoG91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/AmanoBK90,
author = {Hideharu Amano and
Taisuke Boku and
Tomohiro Kudoh},
title = {(SM){\({^2}\)}-II: {A} Large-Scale Multiprocessor for Sparse Matrix
Calculations},
journal = {{IEEE} Trans. Computers},
volume = {39},
number = {7},
pages = {889--905},
year = {1990},
url = {https://doi.org/10.1109/12.55691},
doi = {10.1109/12.55691},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/AmanoBK90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/Amano90,
author = {Hideharu Amano},
editor = {Benjamin W. Wah},
title = {A Fault Tolerant Batcher Network},
booktitle = {Proceedings of the 1990 International Conference on Parallel Processing,
Urbana-Champaign, IL, USA, August 1990. Volume 1: Architecture},
pages = {441--444},
publisher = {Pennsylvania State University Press},
year = {1990},
timestamp = {Mon, 28 Jul 2014 17:06:01 +0200},
biburl = {https://dblp.org/rec/conf/icpp/Amano90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ifip/AmanoTK89,
author = {Hideharu Amano and
Takuya Terasawa and
Tomohiro Kudoh},
editor = {Gerhard X. Ritter},
title = {Cache with Synchronization Mechanism},
booktitle = {Information Processing 89, Proceedings of the {IFIP} 11th World Computer
Congress, San Francisco, USA, August 28 - September 1, 1989},
pages = {1001--1006},
publisher = {North-Holland/IFIP},
year = {1989},
timestamp = {Wed, 02 Feb 2022 21:17:54 +0100},
biburl = {https://dblp.org/rec/conf/ifip/AmanoTK89.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwdm/MiyazakiTAA89,
author = {Jun Miyazaki and
Kenji Takeda and
Hideharu Amano and
Hideo Aiso},
editor = {Haran Boral and
Pascal Faudemay},
title = {A New Version of a Parallel Production System Machine, {MANJI-II}},
booktitle = {Database Machines, Sixth International Workshop, {IWDM} '89, Deauville,
France, June 19-21, 1989, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {368},
pages = {317--330},
publisher = {Springer},
year = {1989},
url = {https://doi.org/10.1007/3-540-51324-8\_44},
doi = {10.1007/3-540-51324-8\_44},
timestamp = {Tue, 14 May 2019 10:00:42 +0200},
biburl = {https://dblp.org/rec/conf/iwdm/MiyazakiTAA89.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/parle/LingA89,
author = {Xiao{-}ping Ling and
Hideharu Amano},
editor = {Eddy Odijk and
Martin Rem and
Jean{-}Claude Syre},
title = {A static scheduling system for a parallel machine (SM)\({}^{\mbox{2}}\)-II},
booktitle = {{PARLE} '89: Parallel Architectures and Languages Europe, Volume {I:}
Parallel Architectures, Eindhoven, The Netherlands, June 12-16, 1989,
Proceedings},
series = {Lecture Notes in Computer Science},
volume = {365},
pages = {118--135},
publisher = {Springer},
year = {1989},
url = {https://doi.org/10.1007/3540512845\_36},
doi = {10.1007/3540512845\_36},
timestamp = {Tue, 14 May 2019 10:00:52 +0200},
biburl = {https://dblp.org/rec/conf/parle/LingA89.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/BokuNA88,
author = {Taisuke Boku and
Shigehiro Nomura and
Hideharu Amano},
editor = {Howard Jay Siegel},
title = {{IMPULSE:} {A} High Performance Processing Unit for Multiprocessors
for Scientific Calculation},
booktitle = {Proceedings of the 15th Annual International Symposium on Computer
Architecture, Honolulu, Hawaii, USA, May-June 1988},
pages = {365--372},
publisher = {{IEEE} Computer Society},
year = {1988},
url = {https://doi.org/10.1109/ISCA.1988.5247},
doi = {10.1109/ISCA.1988.5247},
timestamp = {Thu, 08 Jul 2021 16:04:01 +0200},
biburl = {https://dblp.org/rec/conf/isca/BokuNA88.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwdm/MiyazakiATA87,
author = {Jun Miyazaki and
Hideharu Amano and
Kenji Takeda and
Hideo Aiso},
editor = {Masaru Kitsuregawa and
Hidehiko Tanaka},
title = {A Shared Memory Architecture for {MANJI} Production System Machine},
booktitle = {Database Machines and Knowledge Base Machines, 5th International Workshop
on Database Machines, Tokyo, Japan, 1987, Proceedings},
series = {The Kluwer International Series in Engineering and Computer Science},
volume = {43},
pages = {517--531},
publisher = {Kluwer},
year = {1987},
url = {https://doi.org/10.1007/978-1-4613-1679-4\_37},
doi = {10.1007/978-1-4613-1679-4\_37},
timestamp = {Fri, 19 May 2017 01:25:51 +0200},
biburl = {https://dblp.org/rec/conf/iwdm/MiyazakiATA87.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/YokotaAA86,
author = {Takashi Yokota and
Hideharu Amano and
Hideo Aiso},
title = {Dynamic fault recovery in mesh-connected parallel computers},
journal = {Syst. Comput. Jpn.},
volume = {17},
number = {7},
pages = {10--18},
year = {1986},
url = {https://doi.org/10.1002/scj.4690170702},
doi = {10.1002/SCJ.4690170702},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/YokotaAA86.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/conpar/SaitoAKA86,
author = {Chizuko Saito and
Hideharu Amano and
Tomohiro Kudoh and
Hideo Aiso},
editor = {Wolfgang H{\"{a}}ndler and
Dieter Haupt and
Rolf Jeltsch and
Wilfried Juling and
Otto Lange},
title = {An Adaptable Cluster Structure of (SM){\({^2}\)}-II},
booktitle = {{CONPAR} 86: Conference on Algorithms and Hardware for Parallel Processing,
Aachen, Germany, September 17-19, 1986, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {237},
pages = {53--60},
publisher = {Springer},
year = {1986},
url = {https://doi.org/10.1007/3-540-16811-7\_153},
doi = {10.1007/3-540-16811-7\_153},
timestamp = {Tue, 14 May 2019 10:00:55 +0200},
biburl = {https://dblp.org/rec/conf/conpar/SaitoAKA86.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/AmanoCYA85,
author = {Hideharu Amano and
Junji Chikawa and
Takaichi Yoshida and
Hideo Aiso},
title = {Performance analysis of parallel machines using multi-read memory},
journal = {Syst. Comput. Jpn.},
volume = {16},
number = {3},
pages = {29--37},
year = {1985},
url = {https://doi.org/10.1002/scj.4690160304},
doi = {10.1002/SCJ.4690160304},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/AmanoCYA85.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/AmanoBKA85,
author = {Hideharu Amano and
Taisuke Boku and
Tomohiro Kudoh and
Hideo Aiso},
editor = {Thomas F. Gannon and
Tilak Agerwala and
Charles V. Freiman},
title = {(SM){\({^2}\)}-II: {A} New Version of the Sparse Matrix Solving Machine},
booktitle = {Proceedings of the 12th Annual Symposium on Computer Architecture,
Boston, MA, USA, June 1985},
pages = {100--107},
publisher = {{IEEE} Computer Society},
year = {1985},
url = {https://doi.org/10.1145/327070.327137},
doi = {10.1145/327070.327137},
timestamp = {Tue, 31 Aug 2021 17:59:20 +0200},
biburl = {https://dblp.org/rec/conf/isca/AmanoBKA85.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/AmanoYA83,
author = {Hideharu Amano and
Takaichi Yoshida and
Hideo Aiso},
editor = {Harold W. Lawson Jr. and
Tilak Agerwala and
Hans H. Heilborn and
Hideo Aiso and
Lars{-}Erik Thorelli and
Jean{-}Loup Baer and
Mario Tokoro},
title = {{(SM)2:} Sparse Matrix Solving Machine},
booktitle = {Proceedings of the 10th Annual Symposium on Computer Architecture,
1983},
pages = {213--220},
publisher = {{ACM}},
year = {1983},
url = {https://doi.org/10.1145/800046.801658},
doi = {10.1145/800046.801658},
timestamp = {Tue, 13 Jul 2021 10:01:21 +0200},
biburl = {https://dblp.org/rec/conf/isca/AmanoYA83.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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