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Richard J. Eickemeyer
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Books and Theses
- 1988
- [b1]Richard J. Eickemeyer:
Performance Evaluation of Multiple Register Set Architectures and Cache Memories. University of Illinois Urbana-Champaign, USA, 1988
Journal Articles
- 2015
- [j11]R. Raghavan, Richard J. Eickemeyer, Aaron Sawdey, John Griswell, D. Parikh, S. Ramani, D. M. Daly, N. Ni, B. Rogers, Alex E. Mericas, L. Maurice, K. Vu:
IBM POWER8 performance and energy modeling. IBM J. Res. Dev. 59(1) (2015) - [j10]Balaram Sinharoy, James Van Norstrand, Richard J. Eickemeyer, Hung Q. Le, Jens Leenstra, Dung Q. Nguyen, B. Konigsburg, K. Ward, M. D. Brown, José E. Moreira, D. Levitan, S. Tung, David Hrusecky, James W. Bishop, Michael Gschwind, Maarten Boersma, Michael Kroener, Markus Kaltenbach, Tejas Karkhanis, K. M. Fernsler:
IBM POWER8 processor core microarchitecture. IBM J. Res. Dev. 59(1) (2015) - 2008
- [j9]Leland Chang, Robert K. Montoye, Yutaka Nakamura, Kevin Batson, Richard J. Eickemeyer, Robert H. Dennard, Wilfried Haensch, Damir Jamsek:
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches. IEEE J. Solid State Circuits 43(4): 956-963 (2008) - 2005
- [j8]Balaram Sinharoy, Ronald N. Kalla, Joel M. Tendler, Richard J. Eickemeyer, Jody B. Joyner:
POWER5 system microarchitecture. IBM J. Res. Dev. 49(4-5): 505-522 (2005) - [j7]Harry M. Mathis, Alex E. Mericas, John D. McCalpin, Richard J. Eickemeyer, Steven R. Kunkel:
Characterization of simultaneous multithreading (SMT) efficiency in POWER5. IBM J. Res. Dev. 49(4-5): 555-564 (2005) - 2000
- [j6]Steven R. Kunkel, Richard J. Eickemeyer, Mikko H. Lipasti, Timothy J. Mullins, Brian O'Krafka, Harold Rosenberg, Steven P. Vanderwiel, Philip L. Vitale, Larry D. Whitley:
A performance methodology for commercial servers. IBM J. Res. Dev. 44(6): 851-872 (2000) - [j5]John M. Borkenhagen, Richard J. Eickemeyer, Ronald N. Kalla, Steven R. Kunkel:
A multithreaded PowerPC processor for commercial servers. IBM J. Res. Dev. 44(6): 885-898 (2000) - 1994
- [j4]Stamatis Vassiliadis, Bart Blaner, Richard J. Eickemeyer:
SCISM: A scalable compound instruction set machine. IBM J. Res. Dev. 38(1): 59-78 (1994) - 1993
- [j3]Richard J. Eickemeyer, Stamatis Vassiliadis:
A load-instruction unit for pipelined processors. IBM J. Res. Dev. 37(4): 547-564 (1993) - 1992
- [j2]Nadeem Malik, Richard J. Eickemeyer, Stamatis Vassiliadis:
Instruction-level parallelism from execution interlock collapsing. SIGARCH Comput. Archit. News 20(4): 38-43 (1992) - [j1]Stamatis Vassiliadis, Bart Blaner, Richard J. Eickemeyer:
On the attributes of the SCISM organization. SIGARCH Comput. Archit. News 20(4): 44-53 (1992)
Conference and Workshop Papers
- 2021
- [c8]Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose:
Energy Efficiency Boost in the AI-Infused POWER10 Processor. ISCA 2021: 29-42 - 2011
- [c7]Hans M. Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard J. Eickemeyer:
Abstraction and microarchitecture scaling in early-stage power modeling. HPCA 2011: 394-405 - 2005
- [c6]Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler:
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. HPCA 2005: 238-242 - 1997
- [c5]Richard J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Beng-Hong Lim, Mark S. Squillante, Ching-Farn Eric Wu:
Evaluation of Multithreaded Processors and Thread-Switch Policies. ISHPC 1997: 75-90 - 1996
- [c4]Richard J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Mark S. Squillante, Shiafun Liu:
Evaluation of Multithreaded Uniprocessors for Commercial Application Environments. ISCA 1996: 203-212 - 1992
- [c3]Nadeem Malik, Richard J. Eickemeyer, Stamatis Vassiliadis:
Interlock collapsing ALU for increased instruction-level parallelism. MICRO 1992: 149-157 - 1988
- [c2]Richard J. Eickemeyer, Janak H. Patel:
Performance Evaluation of On-Chip Register and Cache Organizations. ISCA 1988: 64-72 - 1987
- [c1]Richard J. Eickemeyer, Janak H. Patel:
Performance Evaluation of Multiple Register Sets. ISCA 1987: 264-271
Informal and Other Publications
- 2015
- [i1]Bülent Abali, Richard J. Eickemeyer, Hubertus Franke, Chung-Sheng Li, Marc Taubenblatt:
Disaggregated and optically interconnected memory: when will it be cost effective? CoRR abs/1503.01416 (2015)
Coauthor Index
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