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M. C. Chinnaiah

Chinnaiah M. C. – Mangali Chinna Chinnaiah

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affiliation: B V Raju Institute of Technology, Department of Electronics and Communication Engineering, Medak, India
affiliation: Nanyang Technological University, School of Computer Science and Engineering, Singapore

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2020 – today

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2024
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Mudasar Basha, Munuswamy Siva Kumar, Mangali Chinna Chinnaiah, Siew-Kei Lam, Thambipillai Srikanthan, Narambhatla Janardhan, Dodde Hari Krishna, Sanjay Dubey:
Hardware Schemes for Smarter Indoor Robotics to Prevent the Backing Crash Framework Using Field Programmable Gate Array-Based Multi-Robots. Sensors 24(6): 1724 (2024)
2023
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Divya Vani G, Srinivasa Rao Karumuri, Chinnaiah M. C., Siew-Kei Lam, Janardhan Narambhatlu, Sanjay Dubey:
Hardware-Efficient Scheme for Trailer Robot Parking by Truck Robot in an Indoor Environment with Rendezvous. Sensors 23(11): 5097 (2023)
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Mudasar Basha, Munuswamy Siva Kumar, Mangali Chinna Chinnaiah, Siew-Kei Lam, Thambipillai Srikanthan, Narambhatla Janardhan, Dodde Hari Krishna, Sanjay Dubey:
A Versatile Approach to Polygonal Object Avoidance in Indoor Environments with Hardware Schemes Using an FPGA-Based Multi-Robot. Sensors 23(23): 9480 (2023)
[c4]
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T. Keerthi, Apurva Kumari, M. C. Chinnaiah, Mudasar Basha, Rama Rao Chekuri, Dodde Hari Krishna, N. Padmavathy:
An Automatic Vehicle Speed Controlling based on Traffic Signs Recognition using Convolutional Neural Network. ICCCNT 2023: 1-9
2021
[j1]
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Apurva Kumari, Subhendu Kumar Sahoo, M. C. Chinnaiah:
Fast and Efficient Visibility Restoration Technique for Single Image Dehazing and Defogging. IEEE Access 9: 48131-48146 (2021)

2010 – 2019

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2018
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M. C. Chinnaiah, T. P. Kausalya Nandan, P. Haritha, Sanjay Dubey, I. A. Pasha:
A New Deliberation of Embedded based Assistive System for Yoga. ISED 2018: 42-47
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G. Divya Vani, M. C. Chinnaiah, Srinivasa Rao Karumuri:
Hardware Scheme for Autonomous Docking Algorithm using FPGA based Mobile Robot. ISED 2018: 110-115
2016
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  - conf/iciis/AbhilashDC16
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R. Abhilash, Sanjay Dubey, M. C. Chinnaiah:
Asic design of low power VLSI architecture for different multiplier algorithms using compressors. ICIIS 2016: 387-392

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