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2010 – 2019
- 2017
[j1]Marco Ceriani
, Simone Secchi, Oreste Villa, Antonino Tumeo, Gianluca Palermo:
Exploring Efficient Hardware Support for Applications with Irregular Memory Patterns on Multinode Manycore Architectures. IEEE Trans. Parallel Distributed Syst. 28(6): 1635-1648 (2017)- 2015
- [b1]Marco Ceriani:
Exploring architectural support for applications with irregular memory patterns on distributed manycore systems. Polytechnic University of Milan, Italy, 2015 - 2013
- [c7]Simone Secchi, Marco Ceriani, Antonino Tumeo, Oreste Villa, Gianluca Palermo, Luigi Raffo:
Exploring hardware support for scaling irregular applications on multi-node multi-core architectures. ASAP 2013: 309-313 - [c6]Marco Ceriani, Gianluca Palermo, Simone Secchi, Antonino Tumeo, Oreste Villa:
Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping. FCCM 2013: 238 - [c5]Marco Ceriani, Simone Secchi, Antonino Tumeo, Oreste Villa, Gianluca Palermo:
Exploring manycore multinode systems for irregular applications with FPGA prototyping. Hot Chips Symposium 2013: 1 - [c4]Marco Ceriani, Simone Secchi, Antonino Tumeo, Oreste Villa:
Prototyping hardware support for irregular applications. RAPIDO 2013: 4:1-4:8 - 2010
- [c3]Marco Ceriani, Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto, Antonino Tumeo:
Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation. GECCO 2010: 1267-1274
2000 – 2009
- 2009
- [c2]Antonino Tumeo, Marco Branca, Lorenzo Camerini, Marco Ceriani, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto:
Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform. ASP-DAC 2009: 317-322 - 2008
- [c1]Antonino Tumeo, Marco Branca, Lorenzo Camerini, Marco Ceriani, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto:
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications. DATE 2008: 1039-1044
Coauthor Index
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