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ORCIDThe Journal of VLSI Signal Processing, Volume 6
Volume 6, Number 1, June 1993
- Hans Peter Graf:
Special issue on VLSI neural networks. 5 - Yuzo Hirai:
Recent VLSI neural networks in Japan. 7-18 - Hans Peter Graf, Eduard Säckinger, Lawrence D. Jackel:
Recent developments of electronic neural nets in North America. 19-31 - Krste Asanovic, Nelson Morgan, John Wawrzynek:
Using simulations of reduced precision arithmetic to design a neuro-microprocessor. 33-44 - Ulrich Ramacher, Jörg Beichter, Nico Brüls:
A general-purpose signal processor architecture for neurocomputing and preprocessing applications. 45-56 - Ji-Chien Lee, Bing J. Sheu, Rama Chellappa:
A mixed-signal VLSI competitive neuroprocessor for video motion detection. 57-66 - Marwan A. Jabri, Stephen Pickard, Philip H. W. Leong
, Y. Xie:
Algorithmic and implementation issues in analog low power learning neural network chips. 67-76 - Yu-jhih Wu, Michael D. Alston, Paul M. Chau:
Dynamic adaptation of quantization thresholds for soft-decision viterbi decoding with a reinforcement learning neural network. 77-84 - Karl-Heinz Zimmermann, Tien-Chien Lee, Sun-Yuan Kung:
On partitioning and fault tolerance issues for neural array processors. 85-94
Volume 6, Number 2, August 1993
- Will Moore, Wayne Luk:
Introduction. 99-100 - Gordon J. Brebner:
Configurable array logic circuits for computing network error detection codes. 101-117 - Les Mintzer:
FIR filters with field-programmable gate arrays. 119-127 - Barry S. Fagin:
Quantitative measurements of FPGA utility in special and general purpose processors. 129-137 - Sean Monaghan:
A gate-level reconfigurable Monte carlo processor. 139-153 - Jouni Isoaho, Jari Pasanen, Olli Vainio, Hannu Tenhunen:
DSP system integration and prototyping with FPGAS. 155-172 - Erik Brunvand:
Using FPGAs to implement self-timed systems. 173-190 - Miriam Leeser, Richard Chapman, Mark D. Aagaard, Mark H. Linderman, Stephan Meier:
High level synthesis and generating FPGAs with the BEDROC system. 191-214
Volume 6, Number 3, December 1993
- Giulio Casagrande, Armando Chiari, Carla Golla, Salvatore Miceli:
Vlsi programmable digital filter for video signal processing. 219-231 - David M. Mandelbaum:
A method for calculation of the square root using combinatorial logic. 233-242 - Tom Chen, Li Zhu:
An expandable column fft architecture using circuit switching networks. 243-257 - Jenn-Dong Sun, Hari Krishna, K.-Y. Lin:
A superfast algorithm for single-error correction in rrns and hardware implementation. 259-269 - Shuvra S. Bhattacharyya, Edward A. Lee:
Scheduling synchronous dataflow graphs for efficient looping. 271-288 - Jos Huisken, Antoine Delaruelle, B. Egberts, P. Eeckhout, Jef L. van Meerbergen:
Synthesis of synchronous communication hardware in a multiprocessor architecture. 289-299 - Miriam Leeser:
High level synthesis and generation FPGAs with the BEDROC system. 7
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