Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDACM Transactions on Reconfigurable Technology and Systems, Volume 13
Volume 13, Number 1, February 2020
- François Serre, Markus Püschel:
DSL-Based Hardware Generation with Scala: Example Fast Fourier Transforms and Sorting Networks. 1:1-1:23 - Nikolaos Alachiotis, Charalampos Vatsolakis, Grigorios Chrysos, Dionisios N. Pnevmatikatos
:
RAiSD-X: A Fast and Accurate FPGA System for the Detection of Positive Selection in Thousands of Genomes. 2:1-2:30 - Sameh Attia, Vaughn Betz:
Feel Free to Interrupt: Safe Task Stopping to Enable FPGA Checkpointing and Context Switching. 3:1-3:27 - Al-Shahna Jamal, Eli Cahill, Jeffrey Goeders, Steven J. E. Wilton:
Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays. 4:1-4:26 - Alexandra Kourfali, Dirk Stroobandt:
In-Circuit Debugging with Dynamic Reconfiguration of FPGA Interconnects. 5:1-5:29
Volume 13, Number 2, June 2020
- Tushar Garg, Saud Wasly, Rodolfo Pellizzoni, Nachiket Kapre:
HopliteBuf: Network Calculus-Based Design of FPGA NoCs with Provably Stall-Free FIFOs. 6:1-6:35 - Nicholas J. Fraser, Philip H. W. Leong:
Kernel Normalised Least Mean Squares with Delayed Model Adaptation. 7:1-7:30 - Maciej Besta, Marc Fischer, Tal Ben-Nun, Dimitri Stanojevic, Johannes de Fine Licht, Torsten Hoefler:
Substream-Centric Maximum Matchings on FPGA. 8:1-8:33 - Kevin E. Murray, Oleg Petelin, Sheng Zhong, Jia Min Wang, Mohamed Eldafrawy, Jean-Philippe Legault, Eugene Sha, Aaron Graham, Jean Wu, Matthew J. P. Walker, Hanqing Zeng, Panagiotis Patros, Jason Luu, Kenneth B. Kent, Vaughn Betz:
VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling. 9:1-9:55 - Yann Delomier, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo:
Model-based Design of Hardware SC Polar Decoders for FPGAs. 10:1-10:27
Volume 13, Number 3, September 2020
- Zhiyuan Shao, Chenhao Liu, Ruoshi Li, Xiaofei Liao, Hai Jin:
Processing Grid-format Real-world Graphs on DRAM-based FPGA Accelerators with Application-specific Caching Mechanisms. 11:1-11:33 - Mohamed Eldafrawy, Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz:
FPGA Logic Block Architectures for Efficient Deep Learning Inference. 12:1-12:34 - Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha:
Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling. 13:1-13:28 - Sebastian Sabogal, Alan D. George, Christopher M. Wilson:
Reconfigurable Framework for Environmentally Adaptive Resilience in Hybrid Space Systems. 14:1-14:32 - Tuan Minh La, Kaspar Matas, Nikola Grunchevski, Khoa Dang Pham, Dirk Koch:
FPGADefender: Malicious Self-oscillator Scanning for Xilinx UltraScale + FPGAs. 15:1-15:31 - Qi Tang, Zhe Wang, Biao Guo, Li-Hua Zhu, Ji-Bo Wei:
Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAs. 16:1-16:24
Volume 13, Number 4, October 2020
- André DeHon:
Introduction to Special Section on FCCM 2019. 17:1-17:2 - Yun Zhou, Dries Vercruyce, Dirk Stroobandt:
Accelerating FPGA Routing Through Algorithmic Enhancements and Connection-aware Parallelization. 18:1-18:26 - Jialiang Zhang, Yue Zha, Nicholas Beckwith, Bangya Liu, Jing Li:
MEG: A RISCV-based System Emulation Infrastructure for Near-data Processing Using FPGAs and High-bandwidth Memory. 19:1-19:24
- Anuj Vaishnav, Khoa Dang Pham, Joseph Powell, Dirk Koch:
FOS: A Modular FPGA Operating System for Dynamic Workloads. 20:1-20:28 - Aggelos D. Ioannou, Konstantinos Georgopoulos, Pavlos Malakonakis, Dionisios N. Pnevmatikatos, Vassilis D. Papaefstathiou, Ioannis Papaefstathiou, Iakovos Mavroidis:
UNILOGIC: A Novel Architecture for Highly Parallel Reconfigurable Systems. 21:1-21:32
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-07-19 19:13 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
