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ORCIDIEEE Micro, Volume 10
Volume 10, Number 1, February 1990
- Emil W. Brown, Anant Agrawal, Trevor Creary, Michael F. Klein, Dave Murata, Joseph Petolino:
Implementing Sparc in ECL. 10-22 - Stephen C. Johnson:
Hot chips and soggy software. 23-26 - Stephen C. Johnson:
The i486 CPU: executing instructions in one clock cycle. 27-36 - Thomas J. Pennello:
Compiler challenges with RISCs. 37-43 - Curtis R. Priem:
Developing the GX graphics accelerator architecture. 44-54 - Mark Birman, Allen Samuels, George Chu, Ting Chuk, Larry Hu, John McLeod, John Barnes:
Developing the WTL3170/3171 Sparc floating-point coprocessors. 55-64 - Robin W. Edenfield, Michael G. Gallup, William Ledbetter Jr., Ralph McGarity, Eric E. Quintana, Russel A. Reininger:
The 68040 processor. I. Design and implementation. 66-78 - Richard H. Stern:
Appropriate and inappropriate legal protection of user interfaces and screen displays. V. How different forms of copyright protection interact with policy. 79-84
Volume 10, Number 2, April 1990
- J. Luu:
Comments on 'A comparison of RISC architectures' by R.S. Piepho and W.S. Wu. 5 - Richard H. Stern:
Micro Law-software patents. 8-11 - Hideto Hidaka, Yoshio Matsuda, Mikio Asakura, Kazuyasu Fujishima:
The cache DRAM architecture: a DRAM with an on-chip cache memory. 14-25 - Katsuyuki Kaneko, Masaitsu Nakajima, Yasuhiro Kakakura, Junji Nishikawa, Ichiro Okabayashi, Hiroshi Kadota:
Processing element design for a parallel computer. 26-38 - Yuji Hatano, Shinichiro Yano, Hiroyuki Mori, Hiroji Yamada, Mikio Hirano, Ushio Kawabe:
A 4-bit, 250-MIPS processor using Josephson technology. 40-55 - Hiraoki Kaneko, Nariko Suzuki, Hiroshi Wabuka, Koji Maemura:
Realizing the V80 and its system support functions. 56-69 - Milan Milenkovic
:
Microprocessor memory management units. 70-85
Volume 10, Number 3, June 1990
- David V. James:
Multiplexed buses: the endian wars continue. 9-21 - Robin W. Edenfield, Michael G. Gallup, William Ledbetter Jr., Ralph McGarity, Eric E. Quintana, Russel A. Reininger:
The 68040 processor. 2. Memory design and chip. 22-35 - Merrick Darley, Bill Kronlage, Dvaid Bural, Bob Churchill, David Pulling, Paul Wang, Rick Iwamoto, Larry Yang:
The TMS390C602A floating-point coprocessor for Sparc systems. 36-47 - Mitch Alsup:
Motorola's 88000 family architecture. 48-66 - Takeshi Kitahara, Taizo Satoh:
The Gmicro/300 32-bit microprocessor. 68-75
Volume 10, Number 4, August 1990
- Roger D. Chamberlain, Mark A. Franklin:
Hierarchical discrete-event simulation on hypercube architectures. 10-20 - Fadi N. Sibai, Karan L. Watson, Mi Lu:
A parallel unification machine. 21-33 - Michael Rumsey, John Sackett:
An ASIC methodology for mixed analog-digital simulation. 34-40 - A. J. van der Hoeven, Alfons A. J. de Lange, Ed F. Deprettere, Patrick M. Dewilde:
A model for the high-level description and simulation of VLSI networks. 41-48 - Kin-Hong Lee, Kwong-Sak Leung, Sin Man Cheang:
A microprogrammable list processor for personal computers. 50-61 - Yousif A. El-Imam, Karima Banat:
Text-to-speech conversion on a personal computer. 62-74
Volume 10, Number 5, October 1990
- David K. Kahaner:
The Pax parallel computer. 5-6 - Edward A. Lee:
Programmable DSPs: a brief overview. 14-16 - Henry Davis, Robert Fine, Denis Regimbal:
Merging data converters and DSPs for mixed-signal processors. 17-27 - Jeffery C. Bier, Edwin E. Goei, Wai H. Ho, Philip D. Lapsley, Maureen P. O'Reilly, Gilbert C. Sih, Edward A. Lee:
Gabriel: a design environment for DSP. 28-45 - Krishna A. Kumar, Brian Petrasko:
Designing a custom DSP circuit using VHDL. 46-53 - Rulph Chassaing, Wayne A. Peterson, Darrell W. Horning:
A TMS320C25-based multirate filter. 54-62 - Guido Albertengo, Riccardo Sisto:
Parallel CRC generation. 63-71 - F. X. Govers III, M. J. Pierson:
On the edge-analysis of transactions and computers. 73-75
Volume 10, Number 6, December 1990
- Pierre America, Ben J. A. Hulshof, Eddy Odijk, Frans Sijstermans, Rob A. H. van Twist, Rogier H. H. Wester:
Parallel computers for advanced information processing. 12-15 - Colin Whitby-Strevens:
Transputers-past, present and future. 16-19 - Guy Haworth, Steve Leunig, Carsten Hammer, Mike Reeve:
The European Declarative System, database, and languages. 20-23 - Peter Rounce, Jose Delgado:
Architectures within the ESPRIT SPAN project. 24-27 - Bernard Angéniol:
Pygmalion: ESPRIT II project 2059, neurocomputing. 28-31
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