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ORCIDMicroprocessors and Microsystems, Volume 63
Volume 63, November 2018
- Tan Yiyu
:
A Hardware-oriented Object Model for Java in an Embedded Processor.
- Louis D. van Harten, Mahsa Mousavi, Roel Jordans, Hamid Reza Pourshaghaghi:
Determining the necessity of fault tolerance techniques in FPGA devices for space missions. 1-10
- Mariem Makni, Smaïl Niar, Mouna Baklouti, Mohamed Abid:
HAPE: A high-level area-power estimation framework for FPGA-based accelerators. 11-27
- Goran Savic, Milan Prokin, Vladimir M. Rajovic, Dragana Prokin:
Efficient one-dimensional forward and inverse discrete wavelet transformers. 28-35
- Zahra Shirmohammadi, Zeinab Mahdavi:
An efficient and low power one-lambda crosstalk avoidance code design for network on chips. 36-45
- Adis Balota, Selma Grebovic, Sreten Skuletic, Tijana Vujicic, Petar Radunovic:
System of connections and transport of data registered from lightning discharges. 46-54
- Mohammad Reza Asadi Kouhanjani, Amir Hossein Jahangir:
Improving hardware Trojan detection using scan chain based ring oscillators. 55-65
- Roberto Giorgi:
Scalable embedded computing through reconfigurable hardware: Comparing DF-Threads, cilk, openmpi and jump. 66-74 - Davorin Kofjac, Radovan Stojanovic, Andrej Kolozvari, Andrej Skraba:
Designing a low-cost real-time group heart rate monitoring system. 75-84
- Gaurav Purohit, Kota Solomon Raju, Vinod Kumar Chaubey:
Transition sequence based Walsh Encoder: A novel power efficient architecture. 98-103 - Mohammad Baharloo, Ahmad Khonsari:
A low-power wireless-assisted multiple network-on-chip. 104-115
- Milorad Papic, Zlatko Bundalo, Dusanka Bundalo, Radovan Stojanovic, Zivorad Kovacevic, Drazen Pasalic, Branimir Cvijic:
Microcomputer based embedded SCADA and RFID systems implemented on LINUX platform. 116-127
- Davide Zoni, Luca Cremona, Alessandro Cilardo, Mirko Gagliardi, William Fornaciari:
PowerTap: All-digital power meter modeling for run-time power monitoring. 128-139
- Ibrahim Mesecan, Ihsan Ömür Bucak, Betim Çiço:
Comparison of histograms of oriented gradients (HOG) and n-Row average subtraction (nRAS) using GprMax. 140-146
- Max Smith-Creasey, Fatema A. Albalooshi, Muttukrishnan Rajarajan:
Continuous face authentication scheme for mobile devices with tracking and liveness detection. 147-157
- Hossein Amiri, Asadollah Shahbahrami, Angela Pohl, Ben H. H. Juurlink:
Performance evaluation of implicit and explicit SIMDization. 158-168 - Ahmad Lashgar, Ehsan Atoofian, Amirali Baniasadi:
TELEPORT: Hardware/software alternative to CUDA shared memory programming. 169-181 - K. C. Cinnati Loi, Seok-Bum Ko:
Flexible elliptic curve cryptography coprocessor using scalable finite field arithmetic blocks on FPGAs. 182-189 - Ali Shahidinejad, Saeed Fathi:
Wireless-assisted multiple network on chip using microring resonators. 190-198
- Mehdi Roozmeh, Luciano Lavagno:
Design space exploration of multi-core RTL via high level synthesis from OpenCL models. 199-208
- Isidora Stankovic, Milos Dakovic, Cornel Ioana:
Decomposition and analysis of signals sparse in the dual polynomial Fourier transform. 209-215
- Oana Boncalo, Gyorgy Kolumban-Antal, David Declercq, Valentin Savin:
Code-design for efficient pipelined layered LDPC decoders with bank memory organization. 216-225 - Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff:
Supporting concurrent memory access in TCF processor architectures. 226-236
- Pedro Henrique Exenberger Becker, Anderson Luiz Sartor, Marcelo Brandalero, Antonio Carlos Schneider Beck:
BRAM-based function reuse for multi-core architectures in FPGAs. 237-248
- Sina Shahhosseini, Kasra Moazzemi, Amir M. Rahmani, Nikil D. Dutt:
On the feasibility of SISO control-theoretic DVFS for power capping in CMPs. 249-258 - Sajjad Nouri, Davide Rossi, Jari Nurmi:
Power mitigation of a heterogeneous multicore architecture on FPGA/ASIC by DFS/DVFS techniques. 259-268
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