default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIntegration, Volume 95
Volume 95, March 2024
- Wei Xiao
, Fazhan Zhao, Kun Zhao, Hongtu Ma, Qing Li:
TA-denseNet: Efficient hardware trust and assurance model based on feature extraction and comparison of SEM images and GDSII images. 102111 - Mahabub Hasan Mahalat, Shyam Subba, Anindan Mondal, Biplab K. Sikdar, Rajat Subhra Chakraborty, Bibhash Sen:
CAPUF: Design of a configurable circular arbiter PUF with enhanced security and hardware efficiency. 102113 - Rahul Chaurasia, Anirban Sengupta:
Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS. 102114 - Sahibia Kaur Vohra, Sherin A. Thomas, Mahendra Sakare, Devarshi Mrinal Das:
Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons. 102122 - Yu Chen, Yongjian Xu, Ning Xu:
Scalable layout decomposition implemented by a distribution evolutionary algorithm. 102125 - Jie Zhang, Jiangang Zuo, Yan Guo, Jinyou Hou, Qinggang Xie:
Nonlinear analysis, circuit implementation, and application in image encryption of a four-dimensional multi-scroll hyper-chaotic system. 102126 - Darío G. Lema, Rubén Usamentiaga, Daniel F. García:
Quantitative comparison and performance evaluation of deep learning-based object detection models on edge computing devices. 102127
- Nikolaos Charalampidis, Apostolos Iatropoulos, Christos K. Volos:
Chaos based speech encryption using microcontroller. 102128 - Lazaros Laskaridis, Christos K. Volos, Hector E. Nistazakis, Efthymia Meletlidou:
Exploring the dynamics of a multistable general model of discrete memristor-based map featuring an exponentially varying memristance. 102131
- Sriram Sundar S, Mahendran G:
CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications. 102132 - Chaudhry Indra Kumar, Abhishek Chaudhary, Shreyansh Upadhyaya:
Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications. 102133
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-06-16 22:53 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
