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Integration, Volume 17

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Volume 17, Number 1, August 1994

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C. Thomas Gray, Wentai Liu, Ralph K. Cavin III, Hong-Yean Hsieh:
Circuit delay calculation considering data dependent delays. 1-23
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  - journals/integration/Kundu94
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Sandip Kundu:
An incremental algorithm for identification of longest (shortest) paths. 25-31
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  - journals/integration/BouletDRR94
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Pierre Boulet, Alain Darte, Tanguy Risset, Yves Robert:
(Pen)-ultimate tiling? 33-51
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Rainer Brück:
Dingo-XT: A technology description language for analog and digital IC layout. 53-81
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Ondrej Sýkora, Imrich Vrt'o:
On VLSI layouts of the star graph and related networks. 83-93
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Volume 17, Number 2, October 1994

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  - journals/integration/Coudert94
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Olivier Coudert:
Two-level logic minimization: an overview. 97-140
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Teofilo F. Gonzalez, Si-Qing Zheng:
Single phase three-layer channel routing algorithms. 141-151
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R. Chandrasekharam, V. V. Vinod, S. Subramanian:
Genetic algorithm for test scheduling with different objectives. 153-161
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Pochang Hsu, Jerzy W. Rozenblit:
A computer-aided design framework for modeling and simulation of VLSI interconnections and packaging. 163-187
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Volume 17, Number 3, November 1994

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Raja Venkateswaran, Pinaki Mazumder:
A survey of DA techniques for PLD and FPGA based systems. 191-240
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Klaus Jansen:
On the complexity of allocation problems in high-level synthesis. 241-252
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Jörg Keller:
Regular layouts of butterfly networks. 253-263
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Sandip Kundu:
An efficient technique for obtaining unate implementation of functions through input encoding. 265-270
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  - journals/integration/SilbermanS94
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Gabriel M. Silberman, Ilan Y. Spillinger:
A backtracing-oriented procedure for the analysis of combinational gate-level designs. 271-286
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