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Integration, Volume 15

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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Volume 15, Number 1, July 1993

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  - journals/integration/AsharDK93
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Pranav Ashar, Srinivas Devadas, Kurt Keutzer:
Path-delay-fault testability properties of multiplexor-based networks. 1-23
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  - journals/integration/AndersonB93
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Mark Anderson, Francine Berman:
Assessing partitioning/ scheduling/storage trade-offs for regular iterative algorithms. 25-50
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  - journals/integration/SuKT93
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S. J. Su, Yue-Sun Kuo, J. C. Tsay:
Adaptable quad tree techniques. 51-71
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  - journals/integration/Molitor93
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Paul Molitor:
A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization. 73-95
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  - journals/integration/Lavenier93
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Dominique Lavenier:
An integrated 2D systolic array for spelling correction. 97-111
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Volume 15, Number 2, October 1993

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  - journals/integration/Wolf93
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Wayne H. Wolf:
FSM decomposition for pipelined data. 117-131
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  - journals/integration/NayakPS93
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Amiya Nayak, Linda Pagli, Nicola Santoro:
Efficient construction of catastrophic patterns for VLSI reconfigurable arrays. 133-150
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  - journals/integration/TragoudasT93
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Spyros Tragoudas, Ioannis G. Tollis:
River routing and density minimization for channels with interchangeable terminals. 151-178
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  - journals/integration/WangW93
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Ting-Chi Wang, D. F. Wong:
Graph-based techniques to speed up floorplan area optimization. 179-199
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  - journals/integration/BuonannoLSS93
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Giacomo Buonanno, Fabrizio Lombardi, Donatella Sciuto, Yinan N. Shen:
Fault detection in TFCMOS/DFCMOS combinational gates. 201-227
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Volume 15, Number 3, October 1993

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  - journals/integration/GopalakrishnanB93
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Ganesh Gopalakrishnan, Erik Brunvand:
Guest editors' introduction to the special issue on asynchronous systems. 233-239
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  - journals/integration/NowickDDH93
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Steven M. Nowick, Mark E. Dean, David L. Dill, Mark Horowitz:
The design of a high-performance cache controller: a case study in asynchronous synthesis. 241-262
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Tam-Anh Chu:
CLASS: a CAD system for automatic synthesis and verification of asynchronous finite state machines. 263-289
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  - journals/integration/NielsenM93
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Christian D. Nielsen, Alain J. Martin:
Design of a delay-insensitive multiply-accumulate unit. 291-311
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  - journals/integration/SparsoS93
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Jens Sparsø, Jørgen Staunstrup:
Delay-insensitive multi-ring structures. 313-340
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  - journals/integration/CoatesDS93
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Bill Coates, Al Davis, Ken Stevens:
The Post Office experience: designing a large asynchronous chip. 341-366
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