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ORCIDIntegration, Volume 1
Volume 1, Number 1, April 1983
- Lambert Spaanenburg:
Editorial. 1 - Christer Svensson:
VLSI physics. 3-19 - Michael Burstein, Richard N. Pelavin:
Hierarchical channel router. 21-38 - Jean Vuillemin:
A very fast multiplication algorithm for VLSI implementation. 39-52 - Satoshi Goto, Tsuneo Matsuda, K. Takamizawa
, Tomyyuki Fujita, H. Mizumura, H. Nakamura, F. Kitajima:
lambda, an integrated master-slice LSI CAD system. 53-69 - G. Grassl, Hans-Jörg Pfleiderer:
A function-independent self-test for large programmable logic arrays. 71-80 - H. J. Wassink, Lambert Spaanenburg:
Logic gate characterization through ringoscillators. 81-85
Volume 1, Numbers 2-3, October 1983
- Lambert Spaanenburg:
Editorial. 105 - Hans K. E. Liesenberg, D. J. Kinniment:
An autolayout system for a hierarchical i.c. design environment. 107-119 - George J. Milne:
Circal: A calculus for circuit description. 121-160 - Jan A. Bergstra, Jan Willem Klop:
A proof rule for restoring logic circuits. 161-178 - Martine D. F. Schlag, Yuh-Zen Liao, C. K. Wong:
An algorithm for optimal two-dimensional compaction of VLSI layouts. 179-209 - Mark G. Karpovsky, Lev B. Levitin:
Detection and identification of input/output stuck-at and bridging faults in combinational and sequential VLSI networks by universal tests. 211-232 - Giuseppe Alia:
VLSI systolic arrays for band matrix multiplication. 233-249
Volume 1, Number 4, December 1983
- Lambert Spaanenburg:
Editorial. 267 - Arne Halaas:
A systolic VLSI matrix for a family of fundamental searching problems. 269-282 - Ralph K. Cavin III, Noel R. Strader:
Microelectronic architectures and devices for signal and symbol processing. 283-304 - Joseph F. JáJá, Robert Michael Owens:
An architecture for a VLSI FFT processor. 305-316 - Magdy A. Bayoumi, Graham A. Jullien, William C. Miller:
An area-time efficient NMOS adder. 317-334 - Christian Piguet:
Design methodology for full custom CMOS microcomputers. 335-350 - Morris Balamut, Ed Kinnen, Rosanne Wyleczuk:
Spice Rack. 351-354
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