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ORCIDNORCAS 2017: Linköping, Sweden
- IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip (SoC), Linköping, Sweden, October 23-25, 2017. IEEE 2017, ISBN 978-1-5386-2844-7
- Guifre Vendrell Pausas, Pere Llimos Muntal
, Ivan H. H. Jørgensen:
High-voltage integrated linear regulator with current sinking capabilities for portable ultrasound scanners. 1-5 - Oscar Morales Chacon, Ted Johansson, Thomas Flink:
The effect of DPD bandwidth limitation on EVM for a 28 nm WLAN 802.11ac transmitter. 1-4 - Oana Boncalo, Valentin Savin, Alexandru Amaricai:
Unrolled layered architectures for non-surjective finite alphabet iterative decoders. 1-5 - Andreas Toftegaard Kristensen, Luca Pezzarossa, Jens Sparsø:
High-level synthesis for reduction of WCET in real-time systems. 1-6 - Heiner Bauer, Sebastian Höppner, Johannes Partzsch, Dennis Walter, Christian Mayr, Florian Schraut, Holger Eisenreich:
Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology. 1-6 - Salma Hesham, Diana Goehringer, Mohamed A. Abd El Ghany:
A call-up for circuit-switched NoCs in the Dark-Silicon Era. 1-6 - Macarena C. Martínez-Rodríguez, Miguel Ángel Prada-Delgado, Piedad Brox, Iluminada Baturone:
CMOS digital design of a trusted virtual sensor. 1-5 - Steve Ngueya W., Julien Mellier, Stephane Ricard, Jean-Michel Portal, Hassen Aziza:
Power efficiency optimization of charge pumps in embedded low voltage NOR flash memory. 1-5 - Harry Weber, Gerald Alexander Koroa, Wolfgang Mathis, Dimitar Delchev, Galia Marinova:
A self-consistent Carleman linearization approach for the design of RF mixer circuits. 1-4 - Xuefei You, Amir Zjajo, Sumeet S. Kumar, Rene van Leuken:
Energy-efficient neuromorphic receptors for wide-range temporal patterns of post-synaptic responses. 1-6 - Alexander Antonov, Pavel Kustarev, Sergey Bikovsky:
Improving microarchitecture design and hardware generation using micro-language IP cores. 1-6 - Shahzad Asif, Mark Vesterbacka:
An RNS based modular multiplier with reduced complexity. 1-4 - Mohammadreza Nakhkash, Hossein Bardareh, Farzaneh Zokaee, Hamid R. Zarandi:
Designing a differential 3R-2bit RRAM cell for enhancing read margin in cross-point RRAM arrays. 1-6 - Bhavin Odedara, Srikanth Bojja, Nitin Gupta, Igor Rapoport, Tony Ross, Alik Zelichenok:
A 1.8mW 450-900MHz ±15ps period jitter programmable multi-output clock generator with high supply noise tolerance in 28-nm CMOS process. 1-4 - Oner Hanay, Erkan Bayram, Renato Negra:
Digital centric IF-DAC based heterodyne transmitter architecture. 1-4 - Franz Marcus Schüffny, Michel Hayoz, Cheolyong Bae, Ishan Arya, Madhur Gokhale, Annapragada Hema Chandar, Martin Nielsen-Lönn, Pavel Angelov:
Zero-crossing detector for a piezoelectric energy harvester. 1-6 - Alok Sethi, Janne P. Aikio, Rana Azhar Shaheen, Rehman Akbar, Timo Rahkonen, Aarno Pärssinen:
A 10-bit active RF phase shifter for 5G wireless systems. 1-4 - Iancu Somesanu, Hermann Schumacher:
A highly compact, 16.8 dBm Pgat Ka-band power amplifier in 250 nm SiGe: C BiCMOS. 1-4 - Kalle Ngo, Tage Mohammadat, Johnny Öberg:
Towards a single event upset detector based on COTS FPGA. 1-6 - Aditya Dalakoti, Merritt Miller, Forrest Brewer:
Design and analysis of high performance pulse ring VCO. 1-5 - Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff:
Supporting concurrent memory access in TCF-aware processor architectures. 1-6 - Jingui Li, Timo Viitanen, Lin Li, Jarmo Takala, Shuvra S. Bhattacharyya:
Design and implementation of a multi-mode harris corner detector architecture. 1-6 - Priit Ruberg, Keijo Lass, Elvar Liiv, Peeter Ellervee:
Performance estimation of embedded applications on microcontrollers. 1-6 - Mina Niknafs, Ivan Ukhov, Petru Eles, Zebo Peng:
Workload prediction for runtime resource management. 1-5 - Henning Puttnies, Christoph Niemann, Sascha Rohde, Dirk Timmermann, Joerg Schacht:
Towards software performance estimation based on register-transfer level descriptions. 1-6 - Pavel Angelov, Martin Nielsen-Lönn, Atila Alvandpour:
Ring-oscillator-based timing generator for ultralow-power applications. 1-4 - Timm Ostermann:
ESD induced EMS problems in digital IOs. 1-6 - Eleftherios Kyriakakis, Kalle Ngo, Johnny Öberg:
Implementation of a fault-tolerant, globally-asynchronous-locally-synchronous, inter-chip NoC communication bridge on FPGAs. 1-6 - Sohaib A. Qazi, Syed Asmat Ali Shah, Hammad Omer, J. Jacob Wikner:
A high-resolution reconfigurable sigma-delta Digital-to-Analog Converter for RF pulse transmission in MRI scanners. 1-6 - Maya Matsunaga, Taiki Nakanishi, Atsuki Kobayashi, Kazuo Nakazato, Kiichi Niitsu:
Three-dimensional millimeter-wave frequency-shift-based CMOS biosensor using vertically stacked LC oscillators. 1-6 - Raju Ahamed, Mikko Varonen, Dristy Parveg, Jan Saijets, Kari Halonen:
Design of high-performance E-band SPDT switch and LNA in 0.13 μm SiGe BiCMOS technology. 1-5 - Yue Lu, Tom J. Kazmierski:
Variable-accuracy bit-serial multiplication with row bypassing for ultra low power. 1-6 - Martin Nielsen-Lönn, Pavel Angelov, J. Jacob Wikner, Atila Alvandpour:
Self-oscillating multilevel switched-capacitor DC/DC converter for energy harvesting. 1-5 - Eleftherios Kyriakakis, Kalle Ngo, Johnny Öberg:
Mitigating single-event upsets in COTS SDRAM using an EDAC SDRAM controller. 1-6 - J. Håvard H. Eriksrød, Kristian Gjertsen Kjelgård, Mathias Tømmer, John F. Burkhart, Tor Sverre Lande:
Bi-static environmental SAR radar imager. 1-6 - Mehdi Roozmeh, Luciano Lavagno:
Implementation of a performance optimized database join operation on FPGA-GPU platforms using OpenCL. 1-6 - Christian Johansson, Torbjorn Manefjord:
Analysis of a high-speed PCB design. 1-4 - Sina Shahhosseini, Kasra Moazzemi, Amir M. Rahmani, Nikil D. Dutt:
Dependability evaluation of SISO control-theoretic power managers for processor architectures. 1-6 - Luca Pezzarossa, Andreas Toftegaard Kristensen, Martin Schoeberl, Jens Sparsø:
Can real-time systems benefit from dynamic partial reconfiguration? 1-6 - Jia Sun, Timo Rahkonen:
Active charge pumping power-saving technique for SC integrators. 1-4 - Keisuke Inoue:
A dependable ASIC architecture with RT-level rollback for controller soft error recovery. 1-4 - Sajjad Nouri, Jari Nurmi:
Power mitigation of a heterogeneous multicore architecture by frequency scaling in an OFDM receiver test case. 1-6 - Jiri Vavra:
A capacitance multiplier based on DBTA. 1-5 - Rana Azhar Shaheen, Rehman Akbar, Alok Sethi, Janne P. Aikio, Timo Rahkonen, Aarno Pärssinen:
A 45nm CMOS SOI, four element phased array receiver supporting two MIMO channels for 5G. 1-4 - P. Ostrovsky, Klaus Tittelbach-Helmrich, Frank Herzel, Oliver Schrape, Gunter Fischer, Dietmar Kissinger, P. Borner, A. Loose, D. Hellmann, P. Hartogh:
A single chip 16 GS/s arbitrary waveform generator in 0.13 μm BiCMOS technology. 1-4 - Peco Gjurovski, Muh-Dey Wei, Renato Negra:
Subsampling phase-locked loop behavioural modelling approach for phase noise evaluation. 1-4 - Henrik Enggaard Hansen, Emad Jacob Maroun, Andreas Toftegaard Kristensen, Jimmi Marquart, Martin Schoeberl:
A shared scratchpad memory with synchronization support. 1-6 - Janne P. Aikio, Alok Sethi, Rana Azhar Shaheen, Rehman Akbar, Timo Rahkonen, Aarno Pärssinen:
A fully integrated 13 GHz CMOS SOI stacked power amplifier for 5G wireless systems. 1-4 - Jeppe Gaardsted Davidsen, Yoni Yosef-Hay, Dennis Oland Larsen, Ivan H. H. Jørgensen:
Synthesis and design of a fully integrated multi-topology switched capacitor DC-DC converter with gearbox control. 1-6
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