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ORCID20th MTV 2019: Austin, TX, USA
- 20th International Workshop on Microprocessor/SoC Test, Security and Verification, MTV 2019, Austin, TX, USA, December 9-10, 2019. IEEE 2019, ISBN 978-1-7281-5025-3
Technical Papers
- Ahmed Wahba, Justin Hohnerlein, Farhan Rahman:
Expediting Design Bug Discovery in Regressions of x86 Processors Using Machine Learning. 1-6 - Mikhail M. Chupilko, Alexander Kamkin
, Alexander Protsenko:
Open-Source Validation Suite for RISC-V. 7-12 - Jinsae Jung, Jaeun Park, Apurva Kumar:
A Verification Framework of Neural Processing Unit for Super Resolution. 13-17 - Mir Tanjidur Rahman, Navid Asadizanjani:
Backside Security Assessment of Modern SoCs. 18-24 - Annachiara Ruospo, Ernesto Sánchez:
On the Detection of Always-On Hardware Trojans Supported by a Pre-Silicon Verification Methodology. 25-30 - Sherif Hosny, Amr Baher:
Design Crawler: A Web Application for Digital Design Metadata Analysis. 31-34 - Jigar Savla:
Smarter Disk Space Management for Silicon Workflows. 35-40 - Jeff Scott, Jonathan Sadowsky, Jigar Savla:
RamGen: Moving Memories from Physical to the Logical Domain. 41-44 - Sankaran M. Menon, Ashish Gupta, Chinna Prudvi, Rolf Kühnis, Sukhbinder Singh Takhar, Spencer K. Millican, Eric Rentschler, Pandy Kalimuthu, Preeti Ranjan Panda, Priyadarsan Patra:
Techniques for Debug of Low Power SoCs. 45-49 - Kejun Chen, Qingxu Deng, Yumin Hou, Yier Jin, Xiaolong Guo:
Hardware and Software Co-Verification from Security Perspective. 50-55 - Ali Shuja Siddiqui, Geraldine Shirley, Sam Reji Joseph, Yutian Gui, Jim Plusquellic, Marten van Dijk, Fareena Saqib:
Multilayer Camouflaged Secure Boot for SoCs. 56-61 - Chetas Mapara, Jerrin Jose:
Automated Test Picker for Complex Microprocessor Verification Environment. 62-64 - Prokash Ghosh, Rohit Srivastava:
Case Study: SoC Performance Verification and Static Verification of RTL Parameters. 65-72 - Gaurav Rajavendra Reddy, Yiorgos Makris:
Design Space Exploration for Hotspot Detection. 73-77
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