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17th MICRO 1984: New Orleans, Louisiana, USA
- M. Carter, Robert A. Mueller:
Proceedings of the 17th annual workshop on Microprogramming, MICRO 1984, New Orleans, Louisiana, USA, October 30 - November 2, 1984. ACM/IEEE 1984 - Veljko Milutinovic, D. Roberts, Kai Hwang:
Mapping HLL constructs into microcode for improved execution speed. 2-11 - Clifford L. Hall:
A microcoded multiprocessor crossbar network communications controller. 12-20 - Jack N. Fenner, Jeffery A. Schmidt, Houssam A. Halabi, Dharma P. Agrawal:
MASCO: An academic exercise in computer design using microprogramming. 21-30 - J. L. Wilkes:
Architecture of a VLSI multiple ISA emulator. 31-36 - David M. Proulx:
Applications of pipelining to firmware. 37-46 - John F. Brown III, Richard L. Sites:
A chip set microarchitecture for a high-performance VAX implementation. 48-54 - Robert Gries, James A. Woodward:
Software tools used in the development of a VLSI VAX Microcomputer. 55-58 - Sridhar Samudrala, Charles Lo, John F. Brown III, Richard E. Calcagni:
Design verification of a VLSI VAX microcomputer. 59-63 - Will Sherwood:
A prototype engineering tester for microcode and hardware debugging. 64-69 - Richard E. Calcagni, Will Sherwood:
Patchable control store for reduced microcode risk in a VLSI VAX microcomputer. 70-76 - Bogong Su, Shiyuan Ding, Lan Jin:
An improvement of trace scheduling for global microcode compaction. 78-85 - Christos A. Papachriston, James M. Reuter:
Microassembly and area reduction techniques for PLA microcode. 86-94 - Takanobu Baba, Mitsuru Ikeda, Katsuhiro Yamazaki, Kenzo Okuda:
Compaction of two-level microprograms for a multiprocessor computer. 95-104 - Richard P. Atkins:
Improved instruction formation in the exhaustive local microcode compaction algorithm. 105-111 - Colin C. Charlton, D. Jackson, Paul H. Leng:
The generation of simulator-based systems for microcode development. 114-121 - Gary Staas:
TDL: A hardware/microcode test language interpreter. 122-128 - J. Eldridge:
A "metasimulator" for microcoded processors. 129-137 - Bernhard Holtkamp, P. Wagner:
An algorithm for selection of migration candidates. 140-146 - Juha-Matti Heimonen, Juha Heinänen:
Migration implementation by integrating microprogramming and HLL programming. 147-154 - Christos A. Papachristou, Venkata R. Immaneni, D. B. Sarma:
An automatic migration scheme based on modular microcode and structured firmware sequencing. 155-164 - Edward M. Carter, Robert I. Winner:
Transparent microprogramming in support of abstract type oriented dynamic vertical migration. 165-178 - C. D. Ardoin, J. L. Linn, B. W. Reynolds:
The implementation of the attributed recursive descent architecture in VAX-11/780 microcode. 179-189 - Carl Ponder, Yale N. Patt:
Alternative proposals for implementing Prolog concurrently and implications regarding their respective microarchitectures. 192-203 - Evan Tick:
Sequential Prolog machine: Image and host architectures. 204-216 - Tep P. Dobry, Yale N. Patt, Alvin M. Despain:
Design decisions influencing the microarchitecture for a Prolog machine. 217-231 - Beth Levy:
Microcode verification using SDVS-the method and a case study. 234-245 - Leo Marcus, Stephen D. Crocker, Jaisook Landauer:
SDVS: A system for verifying microcode correctness. 246-255 - Kazutoshi Takahashi, Etsuo Takahashi, Tatsushige Bitoh, Takao Sugimoto:
A new universal microprogram converter. 264-266 - Peter Marwedel:
A retargetable compiler for a high-level microprogramming language. 267-274 - Robert A. Mueller, Joseph Varghese, Vicki H. Allan:
Global methods in the flow graph approach to retargetable microcode generation. 275-284 - Robert A. Mueller, Michael R. Duda, Stephen M. O'Haire:
A survey of resource allocation methods in optimizing microcode compilers. 285-295 - Subrata Dasgupta:
A model of clocked micro-architectures for firmware engineering and design automation applications. 298-308 - Deepinder P. Sidhu:
Logic programming applied to hardware design specification and verification. 309-313 - Werner Damm:
An axiomatization of low-level parallelism in microarchitectures. 314-323
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