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ORCID23rd ICPP 1994: North Carolina State University, NC, USA - Volume 1
- Dharma P. Agrawal:
Proceedings of the 1994 International Conference on Parallel Processing, North Carolina State University, NC, USA, August 15-19, 1994. Volume I: Architecture. CRC Press 1994, ISBN 0-8493-2493-9
Interconnection Networks
- Toshihiro Hanawa
, Hideharu Amano, Yoshifumi Fujikawa:
Multistage Interconnection Networks with Multiple Outlets. 1-8 - Young-Keun Park, Gyungho Lee:
A High Throughput Packet-Switching Network with Neural Network Controlled Bypass Queueing and Multiplexing. 9-12 - Prasant Mohapatra, Sheldon Wong, Chita R. Das:
Performance Analysis of Combining Multistage Interconnection Networks. 13-16 - Seung-Woo Seo, Tse-Yun Feng:
A General Inside-Out Routing Algorithm for a Class of Rearrangeable Networks. 17-20 - Michael Jurczyk, Thomas Schwederski, R. Born, Howard Jay Siegel, Seth Abraham:
Strategies for the Massively Parallel Simulation of Interconnection Networks. 21-25
Static Networks
- Laxmi N. Bhuyan, Ashwini K. Nanda, Tahsin Askar:
Performance and Reliability of the Multistage Bus Network. 26-33 - Ahmed El-Amawy, Priyalal Kulasinghe:
Theory of Generalized Branch and Combine Clock Networks. 34-37 - Andrew C. Flavell, Yoshizo Takahashi:
Continuum: A Hybrid Time/Space Communications Paradigm for K-ary N-cubes. 38-41 - Jen-Peng Huang, S. Lakshmivarahan, Sudarshan K. Dhall:
Analysis of Interconnection Networks Based on Cayley Graphs of Strong Generating Sets. 42-45 - Subburajan Ponnuswamy, Vipin Chaudhary:
A Comparative Study of Star Graphs and Rotator Graphs. 46-50
Hierarchical Networks
- Ronald Fernandes, Donald K. Friesen, Arkady Kanevsky:
Efficient Routing and Broadcasting in Recursive Interconnection Networks. 51-58 - Peter Thomas Breznay, Mario Alberto López:
A Class of Static and Dynamic Hierarchical Interconnection Networks. 59-62 - Debashis Basak, Dhabaleswar K. Panda:
Designing Large Hierarchical Multiprocessor Systems under Processor, Interconnection, and Packaging Advancements. 63-66 - V. Carl Hamacher, Hong Jiang:
Comparison of Mesh and Hierarchical Networks for Multiprocessors. 67-71 - Kemal Efe, Antonio Fernández:
Computational Properties of Mesh Connected Trees: Versatile Architectures for Parallel Computation. 72-76
Novel Architectures
- Peter M. Kogge:
EXECUBE - A New Architecture for Scalable MPPs. 77-84 - Richard P. Halverson Jr., Art Lew:
Programming with Functional Memory. 85-92 - William E. Cohen, Henry G. Dietz, J. B. Sponaugle:
Dynamic Barrier Architecture for Multi-Mode Fine Grain Parallelism Using Conventional Processors. 93-96 - Hsiao-chen Chung, Chuan-lin Wu, James Rakes, Peter J. Zievers, Yin-Kuan Lin:
Design and Evaluation of a Multiprocessor Architecture with Decentralized Control. 97-100
Interconnection Networks II
- Fotios K. Liotopoulos, Suresh Chalasani:
Nonblocking Operation of Asymmetrical Clos Networks. 101-108 - Tse-Yun Feng, Yanggon Kim:
A New Tag Scheme and Its Tree Representation for a Shuffle-Exchange Network. 109-112 - B. Park, Karan L. Watson:
On the Rearrangeability of Reverse Shuffle/Exchange Networks. 113-116 - Masashi Sasahara, Jun Terada, Luo Zhou, Kalidou Gaye, Jun-ichi Yamato, Satoshi Ogura, Hideharu Amano:
SNAIL: A Multiprocessor Based on the Simple Serial Synchronized Multistage Interconnection Network Architecture. 117-120 - De-Lei Lee, Kenneth E. Batcher:
On Sorting Multiple Bitonic Sequences. 121-125
Wormhole Routing
- Bing-rung Tsai, Kang G. Shin:
Sequencing of Concurrent Communication Traffic in a Mesh Multicomputer with Virtual Channels. 126-133 - David F. Robinson, Philip K. McKinley, Betty H. C. Cheng:
Optimal Multicast Communication in a Wormhole-Routed Torus Networks. 134-141 - José Duato:
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks. 142-149
Cache I
- Yeimkuan Chang, Laxmi N. Bhuyan, Akhilesh Kumar:
A Distributed Cache Coherence Protocol for Hypercube Multiprocessors. 150-157 - Fong Pong, Per Stenström, Michel Dubois:
An Integrated Methodology for the Verification of Directory-Based Cache Protocols. 158-165 - Fredrik Dahlgren, Per Stenström:
Reducing the Write Traffic for a Hybrid Cache Protocol. 166-173
Communication Issues
- Xiaodong Zhang, Yong Yan:
Latency Analysis of CC-NUMA and CC-COMA Rings. 174-181 - Santosh Pande, Kleanthis Psarris:
Compiling Functional Parallelism on a Family of Different Distributed Memory Architectures. 182-186 - Sesh Venugopal, Vijay K. Naik:
Deadlock Free Asynchronous Communication Strategies for Unstructured Computations on iPSC/860. 187-190 - Vipul Gupta, Eugen Schenfeld:
A Comparative Performance Study of an Interconnection Cached Network. 191-195 - Kanad Ghose, R. Kym Horsell, Nitin K. Singhvi:
Hybrid Multiprocessing in OPTIMUL: A Multiprocessor for Distributed and Shared Memory Multiprocessing with WDM Optical Fiber Interconnections. 196-199
Memory Systems
- Amit Agarwala, Chita R. Das:
A Shared Memory Environment for Hypercubes. 200-207 - Benjamin Gamsa, Orran Krieger, Michael Stumm:
Optimizing IPC Performance for Shared-Memory Multiprocessors. 208-211 - Lizyamma Kurian, Bermjae Choi, Paul T. Hulina, Lee D. Coraor:
Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories. 212-219 - Jae Young Lee, Hee Yong Youn:
PSIM: Periodically Shifted Interleaved Memory System. 220-223
VLSI Based Architechture
- N. Ranganathan, Satish Venugopal:
An Efficient VLSI Architecture for Template Matching. 224-231 - Kenneth N. Ellis, Winser E. Alexander:
Block Data Processing Using Commercial Processors. 232-235 - José Salinas, Fabrizio Lombardi:
Rank Order Filtering on an Array With Faulty Processors. 236-240 - James B. Armstrong, Mark A. Nichols, Howard Jay Siegel, Kenneth H. Casey:
Image Correlation: A Case Study to Examine SIMD/MIMD Trade-offs for Scalable Parallel Algorithms. 241-245 - Chouki Aktouf, Chantal Robach, Guy Mazaré:
Fault-Tolerant Routing Algorithms for a Massively Parallel Machine. 246-249
Cache II
- Qing Yang, Sridhar Adina:
A One's Complement Cache Memory. 250-257 - Ricardo Bianchini, Thomas J. LeBlanc:
Can High Bandwidth and Latency Justify Large Cache Blocks in Scalable Multiprocessors? 258-262 - Chi-Hung Chi:
Compiler Optimization Technique for Data Cache Prefetching Using a Small CAM Array. 263-266 - Randall L. Hyde, Brett D. Fleisch:
Degenerate Sharing. 267-270 - Jeng-Ping Lin, Shih-Chang Wang, Sy-Yen Kuo:
Error Recovery in Parallel Systems of Pipelined Processors with Caches. 271-274
Multithreading/VLIW
- K. Gopinath, M. K. Krishna Narasimhan, Beng-Hong Lim, Anant Agarwal:
Performance of Switch Blocking on Multithreaded Architectures. 275-284 - Shyh-Kwei Chen, W. Kent Fuchs, Wen-mei W. Hwu:
An Analytical Approach to Scheduling Code for Superscalar and VLIW Architectures. 285-292 - Steven Wallace, Nader Bagherzadeh:
Performance Issues of a Superscalar Microprocessor. 293-297 - Andrea Capitanio, Nikil D. Dutt, Alexandru Nicolau:
Partitioning of Variables for Multiple-Register-File VLIW Architectures. 298-301
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