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ORCID24th Hot Chips Symposium 2012: Cupertino, CA, USA
- 2012 IEEE Hot Chips 24 Symposium (HCS), Cupertino, CA, USA, August 27-29, 2012. IEEE 2012, ISBN 978-1-4673-8879-5
- Sébastien Nussbaum:
Hot Chips 2012 AMD "Trinity" APU. 1-40 - Paramesh Gopi, Gaurav Singh, Greg Favor:
X-Gene™: 64-bit ARM CPU and SoC. 1-19 - Rumi Zahir:
Medfield smartphone SOC Intel® Atom Z2460 processor. 1-20 - Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee
, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw:
Centip3De: A 64-core, 3D stacked, near-threshold system. 1-30 - Luca Blessent:
FSM™ femtocell station modem. 1-17 - Sebastian Turullols, Ram Sivaramakrishnan:
SPARC T5: 16-core CMT processor with glueless 1-hop scaling to 8-sockets. 1-37 - George Chrysos:
Intel® Xeon Phi coprocessor (codename Knights Corner). 1-31 - Sean Mao:
ArcSoft multi-frame technologies. 72-81 - Ephrem Wu, Suresh Ramalingam:
FPGAs with 28Gb/s transceivers built with heterogeneous stacked-silicon interconnects. 1-20 - Shankar Lakka:
Xilinx SSI technology concept to silicon development overview. 1-22 - Riko Radojcic:
Roadmap for design and EDA infrastructure for 3D products. 1-21 - Pat Gelsinger:
Cloud transforms it Big Data transforms business. 1-30 - Sanjeev Jahagirdar, George Varghese, Inder Sodhi, Ryan Wells:
Power management of the third generation intel core micro architecture formerly codenamed ivy bridge. 1-49 - Robert Rogenmoser:
Reducing transistor variability for high performance low power chips. 1-19 - Ben Blachnitzky:
Augmented reality. 93-103 - James Bornholt, Todd Mytkowicz, Kathryn S. McKinley:
The model is not enough: Understanding energy consumption in mobile devices. 1-3 - Mike Mantor:
AMD Radeon™ HD 7970 with graphics core next (GCN) architecture. 1-35 - Po-Han Huang, Chi-Hung Lin, Hsien-Ching Hsieh, Huang-Lun Lin, Shing-Wu Tung:
Low power and high performance 3-D multimedia platform. 1-3 - Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Paolo A. Aseron, Howard Wilson, Nitin Borkar:
An IA-32 processor with a wide voltage operating range in 32nm CMOS. 1-37 - Kin-Yip Liu:
High performance and efficient single-chip small cell base station SoC. 1-29 - Ephrem Wu:
Optical backplanes with 3D integrated photonics? 1-20 - Choon Lee:
Hot Chips: Stacking tutorial. 1 - David Flynn:
High performance State Retention with Power Gating applied to CPU subsystems - design approaches and silicon evaluation. 1-3 - Jesse Benson, Ryan Cofell, Chris Frericks, Venkatraman Govindaraju, Chen-Han Ho, Zachary Marzec, Tony Nowatzki, Karu Sankaralingam:
Prototyping the DySER specialization architecture with OpenSPARC. 1-3 - Gagan Gupta, Srinath Sridharan, Gurindar S. Sohi:
Efficient, precise-restartable program execution on future multicores. 1-3 - Neil Trevett:
SOC programming tutorial. 1-71 - Robert Bushey:
ADI's revolutionary BF60x vision focused digital signal processor system on chip: 25 billion operations/sec @ 80 mW and zero bandwidth. 1-24 - David Riddoch, Steve Pope:
FPGA augmented ASICs: The time has come. 1-44 - Jim Steele:
Sensor fusion mobile platform challenges and future directions. 104-114 - Mark Papermaster:
The surround computing ERA. 1-26 - Itay Katz:
Touch-free technology. 82-92 - Ronald G. Dreslinski, Korey Sewell, Thomas Manville, Sudhir Satpathy, Nathaniel Ross Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das, Thomas F. Wenisch, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge:
Swizzle Switch: A self-arbitrating high-radix crossbar for NoC systems. 1-44 - Jeff Rupley:
"Jaguar" AMD's next generation low power x86 core. 1-20 - Takumi Maruyama:
SPARC64™ X: Fujitsu's new generation 16 core processor for the next generation UNIX servers. 1-20 - Michael Parker:
Floating point processing using FPGAs. 1-31 - Masato Uchiyama, Hideho Arakida, Yasuki Tanabe, Tsukasa Ike, Takanori Tamai, Moriyasu Banno:
Visconti2 - a heterogeneous multi-core SoC for image-recognition applications. 1-22 - Jeff Gilbert, Mark Rowland:
The Intel® Xeon® processor E5 family architecture, power efficiency, and performance. 1-25 - Ranganathan Sudhakar:
ProAptiv: Efficient performance on a fully-synthesizable core. 1-27 - Marcus Weldon:
The future of wireless networking. 1-24 - Chung-Lung Shum:
IBM zNext - the 3rd generation high frequency microprocessor chip. 1-18 - Rumi Zahir, Christos Kozyrakis:
Welcome to Hot Chips 24. 1-11
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