default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID20th SLIP@DAC 2018: San Francisco, CA, USA
- Shiyan Hu:
Proceedings of the 20th System Level Interconnect Prediction Workshop, SLIP@DAC 2018, San Francisco, CA, USA, June 23, 2018. ACM 2018 - Xinheng Liu, Dae Hee Kim, Chang Wu, Deming Chen:
Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices. 1:1-1:8 - Kwangsoo Han, Andrew B. Kahng, Christopher Moyes, Alex Zelikovsky
:
A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructions. 2:1-2:8 - Di Gao, Tianhao Shen, Cheng Zhuo:
A design framework for processing-in-memory accelerator. 3:1-3:6 - Ilgweon Kang, Dongwon Park, Changho Han, Chung-Kuan Cheng:
Fast and precise routability analysis with conditional design rules. 4:1-4:8 - Po-Ya Hsu, Chun-Han Yao, Yuwei Wang, Chung-Kuan Cheng:
Adaptive sensitivity analysis with nonlinear power load modeling. 5:1-5:6 - Jaya Dofe, Qiaoyan Yu:
Exploiting PDN noise to thwart correlation power analysis attacks in 3D ICs. 6:1-6:6
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-11-29 00:04 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
