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ORCID5th ASYNC 1999: Barcelona, Spain
- 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 19-22 April 1999, Barcelona, Spain. IEEE Computer Society 1999, ISBN 0-7695-0031-5
Verification Techniques
- Wendy Belluomini, Chris J. Myers
, H. Peter Hofstee:
Verification of Delayed-Reset Domino Circuits Using ATACS. 3-12 - Per Arne Karlsen, Per Torstein Røine:
A Timing Verifier and Timing Profiler for Asynchronous Circuits. 13-
Low Power/Noise
- Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury:
Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. 27-35 - Alexander Taubin, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno:
Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications. 36-
Microprocessor Design
- Jim D. Garside, Stephen B. Furber, S.-H. Chung:
AMULET3 Revealed. 51-59 - Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun:
RAPPID: An Asynchronous Instruction Length Decoder. 60-70 - David W. Lloyd, Jim D. Garside, D. A. Gilbert:
Memory Faults in Asynchronous Microprocessors. 71-
Timing Analysis
- Tod Amon, Henrik Hulgaard:
Symbolic Time Separation of Events. 83-93 - Aiguo Xie, Sangyun Kim, Peter A. Beerel:
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice. 94-107 - Tomohiro Yoneda, Hiroshi Ryu:
Timed Trace Theoretic Verification Using Partial Order Reduction. 108-
Synthesis
- Rajit Manohar, Tak-Kwan Lee, Alain J. Martin:
Projection: A Synthesis Technique for Concurrent Systems. 125-134 - Marc Renaudin, Pascal Vivet, Frédéric Robin:
A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation. 135-144 - Jochen Beister, Gernot Eckstein, Ralf Wollowski:
From STG to Extended-Burst-Mode Machines. 145-
Arbitration
- Bill Coates, Jo C. Ebergen, Jon K. Lexau, Scott Fairbanks, Ian W. Jones, Alex Ridgway, David Money Harris, Ivan E. Sutherland:
A Counterflow Pipeline Experiment. 161-172 - Mark R. Greenstreet, Tarik Ono-Tesfaye:
A Fast, asP*, RGD Arbiter. 173-185 - Mark R. Greenstreet:
Real-Time Merging. 186-
Pushing the Performance Limit
- David A. Kearney:
Theoretical Limits on the Data Dependent Performance of Asynchronous Circuits. 201-207 - Ken S. Stevens, Shai Rotem, Ran Ginosar:
Relative Timing. 208-218 - Oliver Hauck, M. Garg, Sorin A. Huss:
Two-Phase Asynchronous Wave-Pipelines and Their Application to a 2D-DCT. 219-
Theory
- Willem C. Mallon, Jan Tijmen Udding, Tom Verhoeff:
Analysis and Applications of the XDI model. 231-242 - Märt Saarepera, Tomohiro Yoneda:
A Self-Timed Implementation of Boolean Functions. 243-
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