BibTeX record journals/jssc/ZhangTSK14

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@article{DBLP:journals/jssc/ZhangTSK14,
  author       = {Sai Zhang and
                  Jane S. Tu and
                  Naresh R. Shanbhag and
                  Philip T. Krein},
  title        = {A 0.79 pJ/K-Gate, 83{\%} Efficient Unified Core and Voltage Regulator
                  Architecture for Sub/Near-Threshold Operation in 130 nm {CMOS}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {49},
  number       = {11},
  pages        = {2644--2657},
  year         = {2014},
  url          = {https://doi.org/10.1109/JSSC.2014.2354048},
  doi          = {10.1109/JSSC.2014.2354048},
  timestamp    = {Sun, 30 Aug 2020 00:13:50 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ZhangTSK14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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