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BibTeX record conf/isscc/YamashitaMHYYMZ17
@inproceedings{DBLP:conf/isscc/YamashitaMHYYMZ17, author = {Ryuji Yamashita and Sagar Magia and Tsutomu Higuchi and Kazuhide Yoneya and Toshio Yamamura and Hiroyuki Mizukoshi and Shingo Zaitsu and Minoru Yamashita and Shunichi Toyama and Norihiro Kamae and Juan Lee and Shuo Chen and Jiawei Tao and William Mak and Xiaohua Zhang and Ying Yu and Yuko Utsunomiya and Yosuke Kato and Manabu Sakai and Masahide Matsumoto and Hardwell Chibvongodze and Naoki Ookuma and Hiroki Yabe and Subodh Taigor and Rangarao Samineni and Takuyo Kodama and Yoshihiko Kamata and Yuzuru Namai and Jonathan Huynh and Sung{-}En Wang and Yankang He and Trung Pham and Vivek Saraf and Akshay Petkar and Mitsuyuki Watanabe and Koichiro Hayashi and Prashant Swarnkar and Hitoshi Miwa and Aditya Pradhan and Sulagna Dey and Debasish Dwibedy and Thushara Xavier and Muralikrishna Balaga and Samiksha Agarwal and Swaroop Kulkarni and Zameer Papasaheb and Sahil Deora and Patrick Hong and Meiling Wei and Gopinath Balakrishnan and Takuya Ariki and Kapil Verma and Chang Hua Siau and Yingda Dong and Ching{-}Huang Lu and Toru Miwa and Farookh Moogat}, title = {11.1 {A} 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology}, booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC} 2017, San Francisco, CA, USA, February 5-9, 2017}, pages = {196--197}, publisher = {{IEEE}}, year = {2017}, url = {https://doi.org/10.1109/ISSCC.2017.7870328}, doi = {10.1109/ISSCC.2017.7870328}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/isscc/YamashitaMHYYMZ17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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