BibTeX record conf/isscc/NiiYTHIK10

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@inproceedings{DBLP:conf/isscc/NiiYTHIK10,
  author       = {Koji Nii and
                  Makoto Yabuuchi and
                  Yasumasa Tsukamoto and
                  Yuuichi Hirano and
                  Toshiaki Iwamatsu and
                  Yuji Kihara},
  title        = {A 0.5V 100MHz {PD-SOI} {SRAM} with enhanced read stability and write
                  margin by asymmetric {MOSFET} and forward body bias},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
                  Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
                  2010},
  pages        = {356--357},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/ISSCC.2010.5433817},
  doi          = {10.1109/ISSCC.2010.5433817},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/NiiYTHIK10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}