BibTeX record conf/isscc/KooOKKSLKKLOLLLLJJCKHKCK12

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@inproceedings{DBLP:conf/isscc/KooOKKSLKKLOLLLLJJCKHKCK12,
  author       = {Kibong Koo and
                  Sunghwa Ok and
                  Yonggu Kang and
                  Seungbong Kim and
                  Choungki Song and
                  Hyeyoung Lee and
                  Hyungsoo Kim and
                  Yongmi Kim and
                  Jeonghun Lee and
                  Seunghan Oak and
                  Yosep Lee and
                  Jungyu Lee and
                  Joongho Lee and
                  Hyungyu Lee and
                  Jaemin Jang and
                  Jongho Jung and
                  Byeongchan Choi and
                  Yong{-}Ju Kim and
                  Youngdo Hur and
                  Yunsaing Kim and
                  Byong{-}Tae Chung and
                  Yongtak Kim},
  title        = {A 1.2V 38nm 2.4Gb/s/pin 2Gb {DDR4} {SDRAM} with bank group and {\texttimes}4
                  half-page architecture},
  booktitle    = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2012, San Francisco, CA, USA, February 19-23, 2012},
  pages        = {40--41},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISSCC.2012.6176869},
  doi          = {10.1109/ISSCC.2012.6176869},
  timestamp    = {Mon, 11 Jan 2021 16:56:31 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/KooOKKSLKKLOLLLLJJCKHKCK12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}