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Ney Laert Vilar Calazans
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- affiliation: Pontifical Catholic University of Rio Grande do Sul, PUCRS, Brazil
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2020 – today
- 2023
- [c121]Eduardo Pereira, Lucas Luza, Nicolas Moura, Luciano Ost, Ney Calazans, Fernando Gehm Moraes, Rafael Garibotti:
Assessment of Communication Protocols' Latency in Co-processing Robotic Systems. NEWCAS 2023: 1-5 - [c120]Nicolas Moura, Joaquim Lucena, Eduardo Pereira, Ney Calazans, Luciano Ost, Fernando Moraes, Rafael Garibotti:
Assessment of Lightweight Cryptography Algorithms on ARM Cortex-M Processors. SBCCI 2023: 1-6 - [c119]Willian Analdo Nunes, Marcos Luiggi Lemos Sartori, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V. SBCCI 2023: 1-6 - 2022
- [c118]Rodrigo N. Wuerdig, Marcos L. L. Sartori, Brunno A. Abreu, Sergio Bampi, Ney Laert Vilar Calazans:
Mitigating Asynchronous QDI Drawbacks on MAC Operators with Approximate Multipliers. ISCAS 2022: 1269-1273 - [c117]Marcos Luiggi Lemos Sartori, Willian Analdo Nunes, Ney Laert Vilar Calazans:
Enhancing an Asynchronous Circuit Design Flow to Support Complex Digital System Design. SBCCI 2022: 1-6 - 2021
- [c116]Taciano A. Rodolfo, Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans:
Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison. ISCAS 2021: 1-5 - 2020
- [c115]Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans:
A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow. ASYNC 2020: 3-10 - [c114]Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Sergio Bampi, Ney Laert Vilar Calazans:
Leveraging QDI Robustness to Simplify the Design of IoT Circuits. ISCAS 2020: 1-5 - [c113]Paulo H. Vancin, Anderson R. P. Domingues, Marcelo Paravisi, Sergio F. Johann, Ney Laert Vilar Calazans, Alexandre M. Amory:
Towards an Integrated Software Development Environment for Robotic Applications in MPSoCs with Support for Energy Estimations. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c112]Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Ney Laert Vilar Calazans:
Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools. ASYNC 2019: 114-123 - [c111]Rodrigo N. Wuerdig, Marcos L. L. Sartori, Ney Laert Vilar Calazans:
Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT Variations. LASCAS 2019: 137-140 - [c110]Luiz Carlos Moreira, José Fontebasso Neto, Walter Silva Oliveira, Thiago Ferauche, Guilherme Heck, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
An IR-UWB pulse generator using PAM modulation with adaptive PSD in 130nm CMOS process. SBCCI 2019: 34 - 2018
- [j18]Matheus T. Moreira, Peter A. Beerel, Marcos L. L. Sartori, Ney Laert Vilar Calazans:
NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1981-1993 (2018) - 2017
- [c109]Leonardo Rezende Juracy, Felipe B. Lazzarotto, Daniel V. Pigatto, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
XGT4: An industrial grade, open source tester for multi-gigabit networks. ICECS 2017: 252-255 - [c108]Leandro S. Heck, Matheus T. Moreira, Ney Laert Vilar Calazans:
Hardening C-elements against metastability. ICECS 2017: 314-317 - [c107]Marcos L. L. Sartori, Ney Laert Vilar Calazans:
Go functional model for a RISC-V asynchronous organisation - ARV. ICECS 2017: 381-384 - [c106]Ricardo A. Guazzelli, Matheus T. Moreira, Ney Laert Vilar Calazans:
A comparison of asynchronous QDI templates using static logic. LASCAS 2017: 1-4 - [c105]Ricardo A. Guazzelli, Matheus T. Moreira, Walter Lau Neto, Ney Laert Vilar Calazans:
Sleep convention logic isochronic fork: an analysis. SBCCI 2017: 103-109 - 2016
- [j17]Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel:
A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits. ACM J. Emerg. Technol. Comput. Syst. 13(2): 15:1-15:23 (2016) - [j16]Sergio Johann Filho, Matheus T. Moreira, Leandro S. Heck, Ney Laert Vilar Calazans, Fabiano Passuelo Hessel:
A processor for IoT applications: An assessment of design space and trade-offs. Microprocess. Microsystems 42: 156-164 (2016) - [j15]Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Testable MUTEX Design. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8): 1188-1199 (2016) - [j14]Ramy N. Tadros, Weizhe Hua, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel:
A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI. IEEE Trans. Circuits Syst. II Express Briefs 63-II(9): 858-862 (2016) - [c104]Ramy N. Tadros, Weizhe Hua, Matheus Gibiluka, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel:
Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. ASYNC 2016: 11-18 - [c103]Carlos Henrique Menezes Oliveira, Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans:
ASCEnD-FreePDK45: An open source standard cell library for asynchronous design. ICECS 2016: 652-655 - [c102]Sergio Johann Filho, Matheus T. Moreira, Ney Laert Vilar Calazans, Fabiano Passuelo Hessel:
The HF-RISC processor: Performance assessment. LASCAS 2016: 95-98 - [c101]Felipe Todeschini Bortolon, Sergio Johann Filho, Matheus Gibiluka, Sergio Bampi, Ney Laert Vilar Calazans, Fabiano Passuelo Hessel, Matheus Trevisan Moreira:
Design and analysis of the HF-RISC processor targeting voltage scaling applications. SBCCI 2016: 1-6 - [c100]Matheus Gibiluka, Matheus Trevisan Moreira, Walter Lau Neto, Ney Laert Vilar Calazans:
A standard cell characterization flow for non-standard voltage supplies. SBCCI 2016: 1-6 - 2015
- [j13]Matheus Trevisan Moreira, Michel Evandro Arendt, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Static Differential NCL Gates: Toward Low Power. IEEE Trans. Circuits Syst. II Express Briefs 62-II(6): 563-567 (2015) - [c99]Dylan Hand, Matheus Trevisan Moreira, Hsin-Ho Huang, Danlei Chen, Frederico Butzke, Zhichao Li, Matheus Gibiluka, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Blade - A Timing Violation Resilient Asynchronous Template. ASYNC 2015: 21-28 - [c98]Dylan Hand, Hsin-Ho Huang, Benmao Cheng, Yang Zhang, Matheus Trevisan Moreira, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Performance Optimization and Analysis of Blade Designs under Delay Variability. ASYNC 2015: 61-68 - [c97]Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Design and Analysis of Testable Mutual Exclusion Elements. ASYNC 2015: 124-131 - [c96]Matheus Gibiluka, Matheus Trevisan Moreira, Ney Laert Vilar Calazans:
A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework. DSD 2015: 79-86 - [c95]Peter A. Beerel, Ney Laert Vilar Calazans:
A path towards average-case silicon via asynchronous resilient bundled-data design. ECCTD 2015: 1-4 - [c94]Matheus T. Moreira, Dylan Hand, Peter A. Beerel, Ney Laert Vilar Calazans:
TDTB error detecting latches: Timing violation sensitivity analysis and optimization. ISQED 2015: 379-383 - [c93]Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel:
A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies. ISVLSI 2015: 27-32 - [c92]Matheus Gibiluka, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
BAT-Hermes: A transition-signaling bundled-data NoC router. LASCAS 2015: 1-4 - [c91]Guilherme Heck, Leandro S. Heck, Matheus T. Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
A digitally controlled oscillator for fine-grained local clock generators in MPSoCs. LASCAS 2015: 1-4 - [c90]Ricardo A. Guazzelli, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Matheus T. Moreira:
SDDS-NCL Design: Analysis of Supply Voltage Scaling. SBCCI 2015: 2:1-2:7 - [c89]Guilherme Heck, Leandro S. Heck, Ajay Singhvi, Matheus T. Moreira, Peter A. Beerel, Ney Laert Vilar Calazans:
Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits. VLSID 2015: 321-326 - 2014
- [j12]Matheus Trevisan Moreira, Guilherme Trojan, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Spatially Distributed Dual-Spacer Null Convention Logic Design. J. Low Power Electron. 10(3): 313-320 (2014) - [j11]Edson I. Moreno, Thais Webber, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
MoNoC: A monitored network on chip with path adaptation mechanism. J. Syst. Archit. 60(10): 783-795 (2014) - [j10]Taciano Perez, Ney Laert Vilar Calazans, César A. F. De Rose:
System-level impacts of persistent main memory using a search engine. Microelectron. J. 45(2): 211-216 (2014) - [j9]Everton Alceu Carara, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Differentiated Communication Services for NoC-Based MPSoCs. IEEE Trans. Computers 63(3): 595-608 (2014) - [j8]Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Beware the Dynamic C-Element. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1644-1647 (2014) - [c88]Matheus T. Moreira, Augusto Neutzling, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas, Ney Calazans:
Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? ASYNC 2014: 53-60 - [c87]Matheus Trevisan Moreira, Michel Evandro Arendt, Ricardo Aquino Guazzelli, Ney Laert Vilar Calazans:
A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design. ASYNC 2014: 93-100 - [c86]Matheus Trevisan Moreira, Ricardo Aquino Guazzelli, Guilherme Heck, Ney Laert Vilar Calazans:
Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis. ACM Great Lakes Symposium on VLSI 2014: 3-8 - [c85]Adriel Ziesemer, Ricardo Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans:
A design flow for physical synthesis of digital cells with ASTRAN. ACM Great Lakes Symposium on VLSI 2014: 245-246 - [c84]Edson I. Moreno, Thais Webber, César A. M. Marcon, Fernando Moraes, Ney Calazans:
A monitored NoC with runtime path adaptation. ISCAS 2014: 1965-1968 - [c83]Matheus T. Moreira, Julian J. H. Pontes, Ney Laert Vilar Calazans:
Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design. ISQED 2014: 692-699 - [c82]Adriel Ziesemer, Ricardo Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans:
Automatic layout synthesis with ASTRAN applied to asynchronous cells. LASCAS 2014: 1-4 - [c81]Ricardo A. Guazzelli, Guilherme Heck, Matheus T. Moreira, Ney Laert Vilar Calazans:
Schmitt trigger on output inverters of NCL gates for soft error hardening: Is it enough? LATW 2014: 1-5 - [c80]Matheus Trevisan, Michel Evandro Arendt, Adriel Ziesemer, Ricardo Augusto da Luz Reis, Ney Laert Vilar Calazans:
Automated Synthesis of Cell Libraries for Asynchronous Circuits. SBCCI 2014: 16:1-16:7 - [c79]Matheus T. Moreira, Ney Laert Vilar Calazans:
Advances on the state of the art in QDI design. VLSI-SoC 2014: 163-164 - 2013
- [c78]Matheus T. Moreira, Bruno S. Oliveira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Charge sharing aware NCL gates design. DFTS 2013: 212-217 - [c77]Matheus Trevisan Moreira, Carlos Henrique Menezes Oliveira, Ney Laert Vilar Calazans, Luciano Copello Ost:
LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries. DSD 2013: 933-940 - [c76]Matheus Trevisan Moreira, Ney Laert Vilar Calazans:
Voltage scaling on C-elements: A speed, power and energy efficiency analysis. ICCD 2013: 329-334 - [c75]Bruno F. Ferreira, Ney Laert Vilar Calazans:
A flexible soft IP core for standard implementations of elliptic curve cryptography in hardware. ICECS 2013: 577-580 - [c74]Julian J. H. Pontes, Ney Calazans, Pascal Vivet:
Parity check for m-of-n delay insensitive codes. IOLTS 2013: 157-162 - [c73]Alexandre M. Amory, Matheus T. Moreira, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Cristiano Lazzari, Marcelo Soares Lubaszewski:
Evaluating the scalability of test buses. ISSoC 2013: 1-6 - [c72]Matheus Trevisan Moreira, Ney Laert Vilar Calazans:
Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow. ISVLSI 2013: 217-218 - [c71]Matheus T. Moreira, Carlos Henrique Menezes Oliveira, Ricardo C. Porto, Ney Laert Vilar Calazans:
Design of NCL gates with the ASCEnD flow. LASCAS 2013: 1-4 - [c70]Matheus T. Moreira, Carlos Henrique Menezes Oliveira, Ricardo C. Porto, Ney Laert Vilar Calazans:
NCL+: Return-to-one Null Convention Logic. MWSCAS 2013: 836-839 - [c69]Matheus T. Moreira, Felipe G. Magalhaes, Matheus Gibiluka, Fabiano Hessel, Ney Laert Vilar Calazans:
BaBaNoC: An asynchronous network-on-chip described in Balsa. RSP 2013: 37-43 - [c68]Yan Ghidini, Matheus T. Moreira, Lucas Brahm, Thais Webber, Ney Calazans, César A. M. Marcon:
Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy. SBCCI 2013: 1-6 - [c67]Julian J. H. Pontes, Ney Calazans, Pascal Vivet:
H2A: A hardened asynchronous network on chip. SBCCI 2013: 1-6 - 2012
- [c66]Julian J. H. Pontes, Ney Calazans, Pascal Vivet:
Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects. ASYNC 2012: 142-149 - [c65]Julian J. H. Pontes, Ney Calazans, Pascal Vivet:
An accurate Single Event Effect digital design flow for reliable system level design. DATE 2012: 224-229 - [c64]Fernando Gehm Moraes, Matheus T. Moreira, Carlos Lucas, D. Correa, Douglas de O. Cardoso, M. Magnaguagno, Guilherme M. Castilhos, Ney Laert Vilar Calazans:
A generic FPGA emulation framework. ICECS 2012: 233-236 - [c63]Matheus T. Moreira, Ney Laert Vilar Calazans:
Electrical characterization of a C-Element with LiChEn. ICECS 2012: 583-585 - [c62]Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans:
Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuits. ICECS 2012: 669-672 - [c61]Taciano Perez, Ney Laert Vilar Calazans, César A. F. De Rose:
A preliminary study on system-level impact of persistent main memory. ISQED 2012: 84-90 - [c60]Matheus T. Moreira, Bruno Cruz de Oliveira, Fernando Moraes, Ney Calazans:
Impact of C-elements in asynchronous circuits. ISQED 2012: 437-343 - [c59]Carlos A. Petry, Eduardo Wächter, Guilherme M. Castilhos, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
A spectrum of MPSoC models for design space exploration and its use. RSP 2012: 30-35 - [c58]Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans:
Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes. SBCCI 2012: 1-6 - [c57]Thiago R. da Rosa, Vivian Larrea, Ney Calazans, Fernando Gehm Moraes:
Power consumption reduction in MPSoCs through DFS. SBCCI 2012: 1-6 - 2011
- [j7]Rafael Iankowski Soares, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Philippe Maurine, Lionel Torres:
A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines. IEEE Des. Test Comput. 28(5): 62-71 (2011) - [j6]César A. M. Marcon, Ney Calazans, Edson I. Moreno, Fernando Moraes, Fabiano Hessel, Altamiro Amadeu Susin:
CAFES: A framework for intrachip application modeling and communication architecture design. J. Parallel Distributed Comput. 71(5): 714-728 (2011) - [c56]Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Fernando Moraes, Ney Calazans:
Adapting a C-element design flow for low power. ICECS 2011: 45-48 - [c55]Juliano Benfica, Letícia Maria Bolzani Poehls, Fabian Vargas, José Lipovetzky, Ariel Lutenberg, Sebastián E. García, Edmundo Gatti, Fernando Hernandez, Ney Laert Vilar Calazans:
Configurable platform for IC combined tests of total-ionizing dose radiation and electromagnetic immunity. LATW 2011: 1-6 - [c54]Edson I. Moreno, César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Arbitration and routing impact on NoC design. International Symposium on Rapid System Prototyping 2011: 193-198 - [c53]Thiago R. da Rosa, Guilherme Montez Guindani, Douglas de O. Cardoso, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
A self-adaptable distributed DFS scheme for NoC-based MPSoCs. SBCCI 2011: 203-208 - [c52]Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Ney Calazans:
A 65nm standard cell set and flow dedicated to automated asynchronous circuits design. SoCC 2011: 99-104 - 2010
- [j5]Ewerson Luiz de Souza Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Dynamic Task Mapping for MPSoCs. IEEE Des. Test Comput. 27(5): 26-35 (2010) - [c51]Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans:
Hermes-A - An Asynchronous NoC Router with Distributed Routing. PATMOS 2010: 150-159 - [c50]Leonel Tedesco, Thiago R. da Rosa, Fabien Clermidy, Ney Calazans, Fernando Gehm Moraes:
Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip. SBCCI 2010: 91-96 - [c49]Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres:
A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks. SBCCI 2010: 115-120 - [c48]Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans:
Hermes-AA: A 65nm asynchronous NoC router with adaptive routing. SoCC 2010: 493-498
2000 – 2009
- 2009
- [c47]Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans:
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA. DATE 2009: 634-639 - [c46]Everton Carara, Roberto P. de Oliveira, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
HeMPS - a Framework for NoC-based MPSoC Generation. ISCAS 2009: 1345-1348 - [c45]Ewerson Carvalho, César A. M. Marcon, Ney Calazans, Fernando Moraes:
Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs. SoC 2009: 87-90 - [c44]Taciano A. Rodolfo, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area. ReConFig 2009: 24-29 - [c43]Guilherme Montez Guindani, Frederico Ferlini, Jeferson Oliveira, Ney Laert Vilar Calazans, Daniel V. Pigatto, Fernando Gehm Moraes:
A 10 Gbps OTN Framer Implementation Targeting FPGA Devices. ReConFig 2009: 30-35 - 2008
- [j4]César Augusto Missio Marcon, Edson Ifarraguirre Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Comparison of network-on-chip mapping algorithms targeting low energy consumption. IET Comput. Digit. Tech. 2(6): 471-482 (2008) - [c42]Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans:
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. ISVLSI 2008: 347-352 - [c41]Guilherme Montez Guindani, Cezar Reinbrecht, Thiago Raupp da Rosa, Ney Calazans, Fernando Gehm Moraes:
NoC Power Estimation at the RTL Abstraction Level. ISVLSI 2008: 475-478 - [c40]Victor Lomné, Thomas Ordas, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans:
Triple Rail Logic Robustness against DPA. ReConFig 2008: 415-420 - [c39]Edson Ifarraguirre Moreno, Katalin Maria Popovici, Ney Laert Vilar Calazans, Ahmed Amine Jerraya:
Integrating Abstract NoC Models within MPSoC Design. IEEE International Workshop on Rapid System Prototyping 2008: 65-71 - [c38]Fernando Gehm Moraes, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans:
MOTIM: an industrial application using nocs. SBCCI 2008: 182-187 - [c37]Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert:
Evaluating the robustness of secure triple track logic through prototyping. SBCCI 2008: 193-198 - 2007
- [c36]Julian J. H. Pontes, Rafael Soares, Ewerson Carvalho, Fernando Moraes, Ney Calazans:
SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. ICCD 2007: 541-546 - [c35]César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Evaluation of Algorithms for Low Energy Mapping onto NoCs. ISCAS 2007: 389-392 - [c34]Erico Bastos, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans, Fernando Moraes:
MOTIM - A Scalable Architecture for Ethernet Switches. ISVLSI 2007: 451-452 - [c33]Ewerson Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload. ISVLSI 2007: 459-460 - [c32]Leandro Möller, Ismael Grehs, Ewerson Carvalho, Rafael Soares, Ney Calazans, Fernando Moraes:
A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems. ReCoSoC 2007: 23-30 - [c31]Luis Carlos Caruso, Guilherme Montez Guindani, Hugo Schmitt, Ney Calazans, Fernando Moraes:
SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems. IEEE International Workshop on Rapid System Prototyping 2007: 27-33 - [c30]Ewerson Carvalho, Ney Calazans, Fernando Moraes:
Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs. IEEE International Workshop on Rapid System Prototyping 2007: 34-40 - [c29]Leonel Tedesco, Fernando Moraes, Ney Calazans:
Buffer sizing for QoS flows in wormhole packet switching NoCs. SBCCI 2007: 99-104 - [c28]Everton Carara, Fernando Moraes, Ney Calazans:
Router architecture for high-performance NoCs. SBCCI 2007: 111-116 - [c27]Aline Mello, Ney Calazans, Fernando Moraes:
QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques. VLSI-SoC (Selected Papers) 2007: 1-22 - [c26]Aline Mello, Ney Laert Vilar Calazans:
Rate-based scheduling policy for QoS flows in networks on chip. VLSI-SoC 2007: 140-145 - [i2]César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel:
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. CoRR abs/0710.4738 (2007) - [i1]Aline Mello, Leandro Möller, Ney Calazans, Fernando Moraes:
MultiNoC: A Multiprocessing System Enabled by a Network on Chip. CoRR abs/0710.4843 (2007) - 2006
- [c25]Leandro Möller, Ismael Grehs, Ney Calazans, Fernando Moraes:
Reconfigurable Systems Enabled by a Network-on-Chip. FPL 2006: 1-4 - [c24]Aline Mello, Leonel Tedesco, Ney Calazans, Fernando Moraes:
Evaluation of current QoS Mechanisms in Networks on Chip. SoC 2006: 1-4 - [c23]Leandro Möller, Rafael Soares, Ewerson Carvalho, Ismael Grehs, Ney Calazans, Fernando Moraes:
Infrastructure for dynamic reconfigurable systems: choices and trade-offs. SBCCI 2006: 44-49 - [c22]Leonel Tedesco, Aline Mello, Leonardo Giacomet, Ney Calazans, Fernando Gehm Moraes:
Application driven traffic modeling for NoCs. SBCCI 2006: 62-67 - 2005
- [c21]Luciano Ost, Aline Mello, José Palma, Fernando Gehm Moraes, Ney Calazans:
MAIA: a framework for networks on chip generation and verification. ASP-DAC 2005: 49-52 - [c20]César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel:
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. DATE 2005: 502-507 - [c19]Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Altamiro Amadeu Susin, Ney Laert Vilar Calazans:
Energy and latency evaluation of NoC topologies. ISCAS (6) 2005: 5866-5869 - [c18]César A. M. Marcon, Márcio Eduardo Kreutz, Altamiro Amadeu Susin, Ney Laert Vilar Calazans:
Models for Embedded Application Mapping onto NoCs: Timing Analysis. IEEE International Workshop on Rapid System Prototyping 2005: 17-23 - [c17]Aline Mello, Leonel Tedesco, Ney Calazans, Fernando Moraes:
Virtual channels in networks on chip: implementation and evaluation on hermes NoC. SBCCI 2005: 178-183 - [c16]Leonel Tedesco, Aline Mello, Diego Garibotti, Ney Calazans, Fernando Moraes:
Traffic generation and performance evaluation for mesh-based NoCs. SBCCI 2005: 184-189 - [c15]José Carlos S. Palma, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Ricardo A. L. Reis, Altamiro Amadeu Susin:
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation. SBCCI 2005: 196-201 - [c14]César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis:
Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. VLSI-SoC 2005: 179-194 - 2004
- [j3]Fernando Gehm Moraes, Ney Calazans, Aline Mello, Leandro Möller, Luciano Ost:
HERMES: an infrastructure for low area overhead packet-switching networks on chip. Integr. 38(1): 69-93 (2004) - [c13]Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes:
MultiNoC: A Multiprocessing System Enabled by a Network on Chip. DATE 2004: 234-239 - [c12]Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato:
FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. FPL 2004: 1042-1046 - [c11]Ewerson Carvalho, Ney Calazans, Eduardo Wenzel Brião, Fernando Moraes:
PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems. SBCCI 2004: 10-15 - 2003
- [c10]Fernando Gehm Moraes, Daniel Mesquita, José Carlos S. Palma, Leandro Möller, Ney Laert Vilar Calazans:
Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs. DATE 2003: 11122-11123 - [c9]Daniel Mesquita, Fernando Gehm Moraes, José Palma, Leandro Möller, Ney Laert Vilar Calazans:
Remote and Partial Reconfiguration of FPGAs: Tools and Trends. IPDPS 2003: 177 - [c8]Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara:
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. SBCCI 2003: 355- - [c7]Fernando Gehm Moraes, Aline Mello, Leandro Möller, Luciano Ost, Ney Laert Vilar Calazans:
A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping. VLSI-SOC 2003: 318-323 - 2002
- [c6]César A. M. Marcon, Fabiano Hessel, Alexandre M. Amory, Luis H. L. Ries, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Prototyping of embedded digital systems from SDL language: a case study. HLDVT 2002: 133-138 - [c5]Alexandre M. Amory, Fernando Moraes, Leandro A. Oliveira, Ney Calazans, Fabiano Hessel:
A Heterogeneous and Distributed Co-Simulation Environment. SBCCI 2002: 115-120 - [c4]José Carlos S. Palma, Aline Vieira de Mello, Leandro Möller, Fernando Moraes, Ney Calazans:
Core Communication Interface for FPGAs. SBCCI 2002: 183-190 - [c3]César Augusto Missio Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Requirements, Primitives and Models for Systems Specification. SBCCI 2002: 323-330 - 2001
- [j2]Ney Laert Vilar Calazans, Fernando Gehm Moraes, Delfim Luiz Torok, Andrey V. Andreoli:
Projeto para Prototipação de um IP Soft Core MAC Ethernet. RITA 8(1): 23-41 (2001) - [j1]Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Integrating the teaching of computer organization and architecture with digital hardware design early in undergraduate courses. IEEE Trans. Educ. 44(2): 109-119 (2001) - [c2]Fernando Moraes, Alexandre M. Amory, Ney Calazans, Eduardo Bezerra, Juracy Petrini:
Using the CAN Protocol and Reconfigurable Computing Technology for Web-Based Smart House Auto. SBCCI 2001: 38-43
1990 – 1999
- 1994
- [c1]Ney Laert Vilar Calazans:
Boolean constrained encoding: a new formulation and a case study. ICCAD 1994: 702-706
Coauthor Index
aka: Ewerson Luiz de Souza Carvalho
aka: Ricardo Aquino Guazzelli
aka: Fabiano Passuelo Hessel
aka: César Augusto Missio Marcon
aka: Marcos Luiggi Lemos Sartori
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