BibTeX records: Mohammed Zackriya V

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@inproceedings{DBLP:conf/fpga/MohanAKZPM21,
  author       = {Prashanth Mohan and
                  Oguz Atli and
                  Onur O. Kibar and
                  V. Mohammed Zackriya and
                  Larry T. Pileggi and
                  Ken Mai},
  editor       = {Lesley Shannon and
                  Michael Adler},
  title        = {Top-down Physical Design of Soft Embedded {FPGA} Fabrics},
  booktitle    = {{FPGA} '21: The 2021 {ACM/SIGDA} International Symposium on Field
                  Programmable Gate Arrays, Virtual Event, USA, February 28 - March
                  2, 2021},
  pages        = {1--10},
  publisher    = {{ACM}},
  year         = {2021},
  url          = {https://doi.org/10.1145/3431920.3439297},
  doi          = {10.1145/3431920.3439297},
  timestamp    = {Wed, 24 Feb 2021 15:58:34 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/MohanAKZPM21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/IsgencMZPP20,
  author       = {Mehmet Meric Isgenc and
                  Mayler G. A. Martins and
                  V. Mohammed Zackriya and
                  Samuel N. Pagliarini and
                  Lawrence T. Pileggi},
  title        = {Logic {IP} for Low-Cost {IC} Design in Advanced {CMOS} Nodes},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {28},
  number       = {2},
  pages        = {585--595},
  year         = {2020},
  url          = {https://doi.org/10.1109/TVLSI.2019.2942825},
  doi          = {10.1109/TVLSI.2019.2942825},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/IsgencMZPP20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/host/SweeneyZPP20,
  author       = {Joseph Sweeney and
                  V. Mohammed Zackriya and
                  Samuel Pagliarini and
                  Lawrence T. Pileggi},
  title        = {Latch-Based Logic Locking},
  booktitle    = {2020 {IEEE} International Symposium on Hardware Oriented Security
                  and Trust, {HOST} 2020, San Jose, CA, USA, December 7-11, 2020},
  pages        = {132--141},
  publisher    = {{IEEE}},
  year         = {2020},
  url          = {https://doi.org/10.1109/HOST45689.2020.9300256},
  doi          = {10.1109/HOST45689.2020.9300256},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/host/SweeneyZPP20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/corr/abs-2005-10649,
  author       = {Joseph Sweeney and
                  Mohammed Zackriya V and
                  Samuel Pagliarini and
                  Lawrence T. Pileggi},
  title        = {Latch-Based Logic Locking},
  journal      = {CoRR},
  volume       = {abs/2005.10649},
  year         = {2020},
  url          = {https://arxiv.org/abs/2005.10649},
  eprinttype    = {arXiv},
  eprint       = {2005.10649},
  timestamp    = {Fri, 22 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/abs-2005-10649.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/VK17,
  author       = {Mohammed Zackriya V and
                  Harish M. Kittur},
  title        = {Content Addressable Memory - Early Predict and Terminate Precharge
                  of Match-Line},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {25},
  number       = {1},
  pages        = {385--387},
  year         = {2017},
  url          = {https://doi.org/10.1109/TVLSI.2016.2576281},
  doi          = {10.1109/TVLSI.2016.2576281},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/VK17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jcsc/ZackriyaK16,
  author       = {V. Mohammed Zackriya and
                  Harish M. Kittur},
  title        = {Low Energy Metric Content Addressable Memory {(CAM)} with Multi Voltage
                  Matchline Segments},
  journal      = {J. Circuits Syst. Comput.},
  volume       = {25},
  number       = {2},
  pages        = {1650002:1--1650002:10},
  year         = {2016},
  url          = {https://doi.org/10.1142/S021812661650002X},
  doi          = {10.1142/S021812661650002X},
  timestamp    = {Tue, 25 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jcsc/ZackriyaK16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ZackriyaK16,
  author       = {V. Mohammed Zackriya and
                  Harish M. Kittur},
  title        = {Precharge-Free, Low-Power Content-Addressable Memory},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {24},
  number       = {8},
  pages        = {2614--2621},
  year         = {2016},
  url          = {https://doi.org/10.1109/TVLSI.2016.2518219},
  doi          = {10.1109/TVLSI.2016.2518219},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ZackriyaK16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jcsc/ZackriyaRHK14,
  author       = {V. Mohammed Zackriya and
                  John Reuben and
                  Ashim Harsh and
                  Harish M. Kittur},
  title        = {Low Power fractional-n frequency Divider with Improved Resolution},
  journal      = {J. Circuits Syst. Comput.},
  volume       = {23},
  number       = {8},
  year         = {2014},
  url          = {https://doi.org/10.1142/S0218126614501126},
  doi          = {10.1142/S0218126614501126},
  timestamp    = {Tue, 25 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jcsc/ZackriyaRHK14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/corr/ZackriyaK14,
  author       = {V. Mohammed Zackriya and
                  Harish M. Kittur},
  title        = {Selective Match-Line Energizer Content Addressable Memory(SMLE -CAM)},
  journal      = {CoRR},
  volume       = {abs/1406.7662},
  year         = {2014},
  url          = {http://arxiv.org/abs/1406.7662},
  eprinttype    = {arXiv},
  eprint       = {1406.7662},
  timestamp    = {Mon, 13 Aug 2018 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/ZackriyaK14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ieiceee/ReubenVNK13,
  author       = {John Reuben and
                  V. Mohammed Zackriya and
                  Salma Nashit and
                  Harish M. Kittur},
  title        = {Capacitance driven clock mesh synthesis to minimize skew and power
                  dissipation},
  journal      = {{IEICE} Electron. Express},
  volume       = {10},
  number       = {24},
  pages        = {20130850},
  year         = {2013},
  url          = {https://doi.org/10.1587/elex.10.20130850},
  doi          = {10.1587/ELEX.10.20130850},
  timestamp    = {Fri, 12 Feb 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ieiceee/ReubenVNK13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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