Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDACM Transactions on Reconfigurable Technology and Systems, Volume 8
Volume 8, Number 1, February 2015
- Stefano Di Carlo
, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta:
SATTA: A Self-Adaptive Temperature-Based TDF Awareness Methodology for Dynamically Reconfigurable FPGAs. 1:1-1:22 - Patrick Cooke, Jeremy Fowers, Greg Brown, Greg Stitt:
A Tradeoff Analysis of FPGAs, GPUs, and Multicores for Sliding-Window Applications. 2:1-2:24 - Heather M. Quinn, Diane Roussel-Dupre, Michael P. Caffrey, Paul S. Graham, Michael J. Wirthlin, Keith Morgan, Anthony Salazar, Tony Nelson, William Howes, Darrel Eric Johnson, Jonathan M. Johnson, Brian H. Pratt, Nathan Rollins, Jim Krone:
The Cibola Flight Experiment. 3:1-3:22 - Tom Davidson, Elias Vansteenkiste, Karel Heyse, Karel Bruneel, Dirk Stroobandt:
Identification of Dynamic Circuit Specialization Opportunities in RTL Code. 4:1-4:24 - Xabier Iturbe, Khaled Benkrid, Chuan Hong, Ali Ebrahim, Raul Torrego, Tughrul Arslan:
Microkernel Architecture and Hardware Abstraction Layer of a Reliable Reconfigurable Real-Time Operating System (R3TOS). 5:1-5:35
Volume 8, Number 2, April 2015
- Kan Shi, David Boland, George A. Constantinides:
Imprecise Datapath Design: An Overclocking Approach. 6:1-6:23 - Louis Woods, Gustavo Alonso, Jens Teubner:
Parallelizing Data Processing on FPGAs with Shifter Lists. 7:1-7:22
- João M. P. Cardoso, Pedro C. Diniz, Katherine (Compton) Morrow:
Guest Editorial FPL 2013. 8:1-8:2 - Ricardo S. Ferreira, Luciana Rocha, André G. Santos, José Augusto Miranda Nacif, Stephan Wong, Luigi Carro:
A Runtime FPGA Placement and Routing Using Low-Complexity Graph Traversal. 9:1-9:16 - Kevin E. Murray, Scott Whitty, Suya Liu, Jason Luu, Vaughn Betz:
Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap between Academic and Commercial CAD. 10:1-10:18 - Lin Gan, Haohuan Fu, Wayne Luk, Chao Yang, Wei Xue, Xiaomeng Huang, Youhui Zhang, Guangwen Yang:
Solving the Global Atmospheric Equations through Heterogeneous Reconfigurable Platforms. 11:1-11:16 - Anup Das, Shyamsundar Venkataraman, Akash Kumar:
Autonomous Soft-Error Tolerance of FPGA Configuration Bits. 12:1-12:17 - Zsolt István, Gustavo Alonso, Michaela Blott, Kees A. Vissers:
A Hash Table for Line-Rate Data Processing. 13:1-13:15
Volume 8, Number 3, May 2015
- Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson:
The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware. 14:1-14:26 - Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu, Oliver Pell:
Automating Elimination of Idle Functions by Runtime Reconfiguration. 15:1-15:28 - Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Wei He:
Exploiting FPGA Block Memories for Protected Cryptographic Implementations. 16:1-16:16 - Juan Fernando Eusse Giraldo, Christopher Williams, Rainer Leupers:
CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design. 17:1-17:16 - Anup Das, Amit Kumar Singh, Akash Kumar:
Execution Trace-Driven Energy-Reliability Optimization for Multimedia MPSoCs. 18:1-18:19 - Yu Ren, Leibo Liu, Shouyi Yin, Jie Han, Shaojun Wei:
Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm. 19:1-19:24 - Roland Dobai, Lukás Sekanina:
Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware. 20:1-20:24
Volume 8, Number 4, October 2015
- Robert Kirchgessner, Alan D. George, Greg Stitt:
Low-Overhead FPGA Middleware for Application Portability and Productivity. 21:1-21:22 - Matthew Jacobsen, Dustin Richmond, Matthew Hogains, Ryan Kastner:
RIFFA 2.1: A Reusable Integration Framework for FPGA Accelerators. 22:1-22:23 - David B. Thomas:
The Table-Hadamard GRNG: An Area-Efficient FPGA Gaussian Random Number Generator. 23:1-23:22 - Zheming Jin, Jason D. Bakos:
Memory Interface Design for 3D Stencil Kernels on a Massively Parallel Memory System. 24:1-24:24 - Guangming Tan, Chunming Zhang, Wendi Wang, Peiheng Zhang:
SuperDragon: A Heterogeneous Parallel System for Accelerating 3D Reconstruction of Cryo-Electron Microscopy Images. 25:1-25:22 - Alexander Biedermann, Sorin A. Huss, Adeel Israr:
Safe Dynamic Reshaping of Reconfigurable MPSoC Embedded Systems for Self-Healing and Self-Adaption Purposes. 26:1-26:22
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-25 04:40 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
