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ORCIDNANOARCH 2012: Amsterdam, The Netherlands
- Csaba Andras Moritz:
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, The Netherlands, July 4-6, 2012. ACM 2012, ISBN 978-1-4503-1671-2
Ambipolar and double gate based architectures
- Kartik Mohanram, Xuebei Yang, Masoud Rostami, Guanxiong Liu, Alexander A. Balandin:
Ambipolar circuits for analog, mixed-signal, and radio-frequency applications. 1-6 - Kotb Jabeur, Ian O'Connor
, Sébastien Le Beux, David Navarro:
Ambipolar double gate CNTFETs based reconfigurable logic cells. 7-13 - Kotb Jabeur, Ian O'Connor, David Navarro, Sébastien Le Beux:
Low-power design technique with ambipolar double gate devices. 14-21
Poster session 1
- Nicolas Chevillon, Morgan Madec, Christophe Lallement:
Gate-level modeling for CMOS circuit simulation with ultimate FinFETs. 22-29 - Yuhao Wang, Hao Yu:
Design exploration of ultra-low power non-volatile memory based on topological insulator. 30-35 - Moein Kianpour, Reza Sabbaghi-Nadooshan:
A conventional design for CLB implementation of a FPGA in quantum-dot cellular automata (QCA). 36-42 - Tanvir Ahmed, Jun Yao, Yasuhiko Nakashima:
Introducing OVP awareness to achieve an efficient permanent defect locating. 43-49 - Ismo Hänninen, Jarmo Takala:
Irreversibility induced density limits and logical reversiblity in nanocircuits. 50-54
Ambipolar, double gate based logic and memories
- Shashikanth Bobba, Pierre-Emmanuel Gaillardon, Jian Zhang, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors. 55-60 - Ian O'Connor, Kotb Jabeur, Sébastien Le Beux, David Navarro:
Ambipolar independent double gate FET logic. 61-68 - Santosh Khasanvis, K. M. Masum Habib, Mostafizur Rahman, Pritish Narayanan, Roger K. Lake, Csaba Andras Moritz:
Ternary volatile random access memory based on heterogeneous graphene-CMOS fabric. 69-76 - Pilin Junsangsri, Fabrizio Lombardi, Jie Han:
Macromodeling a phase change memory (PCM) cell by HSPICE. 77-84
Memristor and crossbar architectures
- Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Damien Querlioz, Djaafar Chabi, Dafine Ravelosona, Claude Chappert, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller:
Crossbar architecture based on 2R complementary resistive switching memory cell. 85-92 - Arne Heittmann, Tobias G. Noll:
A Monte Carlo analysis of a write method used in passive nanoelectronic crossbars. 93-100 - Ogun Turkyilmaz, Santhosh Onkaraiah, Marina Reyboz, Fabien Clermidy, Hraziia, Costin Anghel, Jean-Michel Portal, Marc Bocquet:
RRAM-based FPGA for "normally off, instantly on" applications. 101-108
Reliability and fault tolerance
- Yao Wang, Sorin Dan Cotofana, Liang Fang:
Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices. 109-115 - Nicoleta Cucu Laurenciu, Sorin Dan Cotofana:
A Markovian, variation-aware circuit-level aging model. 116-122 - Saleh Safiruddin, Mihai Lefter, Demid Borodin, George Razvan Voicu, Sorin Dan Cotofana:
Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuits. 123-130 - Jinghang Liang, Jie Han, Linbin Chen, Fabrizio Lombardi:
Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs. 131-138
Poster session 2
- Joseph S. Friedman, Yehea I. Ismail, Gokhan Memik, Alan V. Sahakian, Bruce W. Wessels:
Emitter-coupled spin-transistor logic. 139-145 - Mohamed Amine-Bounouar, Arnaud Beaumont, Khalil El Hajjam, Françis Calmon, Dominique Drouin:
Room temperature double gate single electron transistor based standard cell library. 146-151 - Vikas Sakode, Fabrizio Lombardi, Jie Han:
Cell design and comparative evaluation of a novel 1T memristor-based memory. 152-159 - Stefano Frache, Diego Chiabrando, Mariagrazia Graziano, Fabrizio Riente, Giovanna Turvani, Maurizio Zamboni:
ToPoliNano: nanoarchitectures design made real. 160-167 - Angelo Giuseppe Ruotolo, Marco Ottavi, Salvatore Pontarelli, Fabrizio Lombardi:
A novel write-scheme for data integrity in memristor-based crossbar memories. 168-173
SET, quantum and spintronics computing
- Saleh Safiruddin, Sorin Cotofana, Ferdinand Peper:
Stigmergic search with single electron tunneling technology based memory enhanced hubs. 174-180 - Alexandru Paler, Simon J. Devitt, Kae Nemoto, Ilia Polian:
Synthesis of topological quantum circuits. 181-187 - Nishant Nukala, Niranjan Kulkarni, Sarma B. K. Vrudhula:
Spintronic threshold logic array (STLA) - a compact, low leakage, non-volatile gate array architecture. 188-195 - J. G. Alzate, Parag Upadhyaya, M. Lewis, J. Nath, Y. T. Lin, Kin Wong, S. Cherepov, P. Khalili Amiri, Kang L. Wang, J. Hockel, A. Bur, G. P. Carman, S. Bender, Y. Tserkovnyak, J. Zhu, Y.-J. Chen, I. N. Krivorotov, J. Katine, J. Langer, Prasad Shabadi, Santosh Khasanvis, Sankara Narayanan Rajapandian, Csaba Andras Moritz, Alexander Khitun:
Spin wave nanofabric update. 196-202
Neural computing
- Damien Querlioz, Weisheng Zhao, Philippe Dollfus, Jacques-Olivier Klein, Olivier Bichler, Christian Gamrat:
Bioinspired networks with nanoscale memristive devices that combine the unsupervised and supervised learning approaches. 203-210 - Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy:
Ultra low energy analog image processing using spin based neurons. 211-217 - Michael Soltiz, Cory E. Merkel, Dhireesha Kudithipudi, Garrett S. Rose:
RRAM-based adaptive neural logic block for implementing non-linearly separable functions in a single layer. 218-225 - Manjari S. Kulkarni, Christof Teuscher:
Memristor-based reservoir computing. 226-232
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