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ORCIDDASIP 2014: Madrid, Spain
- Eduardo de la Torre, Sébastien Pillement:
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, DASIP 2014, Madrid, Spain, October 8-10, 2014. IEEE 2014, ISBN 979-10-92279-06-1
Session 1: Wearable computing, compressed sensing, and communication
- Daniele Bortolotti
, Mauro Mangia, Andrea Bartolini, Riccardo Rovatti, Gianluca Setti, Luca Benini:
Rakeness-based compressed sensing on ultra-low power multi-core biomedicai processors. 1-8 - Koldo Basterretxea, Javier Echanobe, Inés del Campo:
A wearable human activity recognition system on a chip. 1-8 - Lukas Meder, Philipp C. Schindler, Amos Agmon, Maxim Meltsin, Rene Bonk, Joachim Meyer, Michael Dreschmann, Alex Tolmachev, Rolf B. Hilgendorf, Moshe Nazarathy, Shalva Ben-Ezra, Thomas Pfeiffer, Wolfgang Freude, Juerg Leuthold, Christian Koos, Jürgen Becker:
Flexible real-time transmitter at 10 Gbit/s for SCFDMA PONs focusing on low-cost ONUs. 1-8
Session 2: Hardware, FPGAs, and reconfigurable hardware
- Farid Shamani, Roberto Airoldi, Tapani Ahonen, Jari Nurmi:
FPGA implementation of a flexible synchronizer for cognitive radio applications. 1-8 - Andreas Erik Hindborg, Pascal Schleuniger, Nicklas Bo Jensen, Sven Karlsson:
Hardware realization of an FPGA processor - Operating system call offload and experiences. 1-8 - Carlo Sau, Francesca Palumbo:
Automatic generation of dataflow-based reconfigurable co-processing units. 1-8 - Lionel Vincent, Stéphane Mancini:
Closed-loop adaptive and stochastic prefetch mechanism for data array. 1-8
Session 3 (Special session): Arithmetic for image and signal processing
- Riham Nehmeh, Daniel Ménard, Andrei Banciu, Thierry Michel, Romuald Rocher:
A fast method for overflow effect analysis in fixed-point systems. 1-6 - Matthieu Martel, Amine Najahi, Guillaume Revy:
Toward the synthesis of fixed-point code for matrix inversion based on Cholesky decomposition. 1-8 - Tomasz Kryjak, Jorge Portilla:
Demo night. 1 - Julien Heulot, Judicael Menant, Maxime Pelcat, Jean-François Nezan, Luce Morin, Muriel Pressigout, Slaheddine Aridhi:
Demonstrating a dataflow-based RTOS for heterogeneous MPSoC by means of a stereo matching application. 1-2 - Yaset Oliva, Emmanuel Casseau, Kevin J. M. Martin, Pierre Bomel, Jean-Philippe Diguet, Hervé Yviquel, Mickaël Raulet, Erwan Raffin, Laurent Morin:
Orcc's compa-backend demonstration. 1-2 - Miguel A. Prada-Delgado, Susana Eiroa, Iluminada Baturone:
Robust unclonable identifiers and true random numbers from off-the-shelf SRAMs. 1-2 - Simone Casale Brunet, M. Wiszniewska, Endri Bezati, Marco Mattavelli, Jörn W. Janneck, Massimo Canale:
TURNUS: An open-source design space exploration framework for dynamic stream programs. 1-2
Session 4 (Special session): Visual scene analysis on hybrid multicore
- Johny Paul, Walter Stechele, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert, Tamim Asfour:
Self-adaptive harris corner detector on heterogeneous many-core processor. 1-8 - Giuseppe Tagliavini, Germain Haugou, Luca Benini:
Optimizing memory bandwidth in OpenVX graph execution on embedded many-core accelerators. 1-8 - Tomasz Kryjak, Mateusz Komorkiewicz, Marek Gorgon:
Hardware-software implementation of vehicle detection and counting using virtual detection lines. 1-8 - Hamza Bendaoudi, Farida Cheriet, Houssem Ben Tahar, J. M. Pierre Langlois:
A scalable hardware architecture for retinal blood vessel detection in high resolution fundus images. 1-6
Session 5: Frameworks and model transformations
- Michael Mefenza, Franck Yonga, Luca Bochi Saldanha, Christophe Bobda, Senem Velipasalar:
A framework for rapid prototyping of embedded vision applications. 1-8 - Manel Ammar, Mouna Baklouti, Maxime Pelcat, Karol Desnos, Mohamed Abid:
MARTE to ΠSDF transformation for data-intensive applications analysis. 1-8 - Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Massimo Canale, Jörn W. Janneck:
Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control. 1-6 - Simon Holmbacka, Erwan Nogues, Maxime Pelcat, Sébastien Lafond, Johan Lilius:
Energy efficiency and performance management of parallel dataflow applications. 1-8
Session 6: Heterogeneous platforms
- Konrad Moren, Thomas Perschke, Diana Göhringer:
Accelerating local feature extraction using OpenCL on heterogeneous platforms. 1-8 - Thorsten Wink, Andreas Koch:
PHAT: A technology for prototyping parallel heterogeneous architectures. 1-8 - Berend H. J. Dekens, Philip S. Wilmanns, Gerard J. M. Smit, Marco Bekooij:
Low-cost guaranteed-throughput dual-ring communication infrastructure for heterogeneous MPSoCs. 1-8 - Thanh Dinh Ngo, Daniel Sepulveda, Kevin J. M. Martin, Jean-Philippe Diguet:
Communication-model based embedded mapping of dataflow actors on heterogeneous MPSoC. 1-8
Poster Session
- Chiraz Trabelsi, Samy Meftali, Rabie Ben Atitallah, Jean-Luc Dekeyser:
Model-driven design flow for distributed control in reconfigurable FPGA systems. 1-6 - Rong Ren, Eduardo Juárez, César Sanz, Mickaël Raulet, Fernando Pescador:
Energy-aware decoders: A case study based on an RVC-CAL specification. 1-6 - Gregor Schewior, Christian Zahl, Holger Blume, Stefan Wonneberger, Jan Effertz:
HLS-based FPGA implementation of a predictive block-based motion estimation algorithm - A field report. 1-8 - Christian Hochberger, Lukas Johannes Jung, Andreas Engel, Andreas Koch:
Synthilation: JIT-compilation of microinstruction sequences in AMIDAR processors. 1-6 - Judicael Menant, Muriel Pressigout, Luce Morin, Jean-François Nezan:
Optimized fixed point implementation of a local stereo matching algorithm onto C66x DSP. 1-6 - Antonio Fuentes-Alventosa, Juan Gómez-Luna, José María González-Linares, Nicolás Guil:
CUVLE: Variable-length encoding on CUDA. 1-6 - Martin Danek, Roman Bartosinski, Christian Hochberger:
Foreground detection in video streams in an FPGA without external memory. 1-6 - Matthieu Garrigues, Antoine Manzanera:
Video++, a modern image and video processing C++ framework. 1-6 - Laurent Cabaret, Lionel Lacassagne, Louiza Oudni:
A review of world's fastest connected component labeling algorithms: Speed and energy estimation. 1-6 - Rosario Arjona, Rocio Romero-Moreno, Iluminada Baturone:
Hardware implementation of a biometric recognition algorithm based on in-air signature. 1-6 - Eugin Hyun, Jonghun Lee:
Hardware architecture design and implementation for FMCW radar signal processing algorithm. 1-6 - Francesco Paci, Davide Brunelli, Luca Benini:
0, 1, 2, many - A classroom occupancy monitoring system for smart public buildings. 1-6 - Aina Randrianarisaina, Olivier Pasquier, Pascal Chargé:
Energy consumption modeling of smart nodes with a function approach. 1-6
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